1 /* 2 * Configuation settings for the Freescale MCF53017EVB. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M53017EVB_H 15 #define _M53017EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 27 28 #define CONFIG_SYS_UNIFY_CACHE 29 30 #define CONFIG_MCFFEC 31 #ifdef CONFIG_MCFFEC 32 # define CONFIG_MII 1 33 # define CONFIG_MII_INIT 1 34 # define CONFIG_SYS_DISCOVER_PHY 35 # define CONFIG_SYS_RX_ETH_BUFFER 8 36 # define CONFIG_SYS_TX_ETH_BUFFER 8 37 # define CONFIG_SYS_FEC_BUF_USE_SRAM 38 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 # define CONFIG_HAS_ETH1 40 41 # define CONFIG_SYS_FEC0_PINMUX 0 42 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 43 # define CONFIG_SYS_FEC1_PINMUX 0 44 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 45 # define MCFFEC_TOUT_LOOP 50000 46 47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 48 # ifndef CONFIG_SYS_DISCOVER_PHY 49 # define FECDUPLEX FULL 50 # define FECSPEED _100BASET 51 # else 52 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # endif 55 # endif /* CONFIG_SYS_DISCOVER_PHY */ 56 #endif 57 58 #define CONFIG_MCFRTC 59 #undef RTC_DEBUG 60 #define CONFIG_SYS_RTC_CNT (0x8000) 61 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 62 63 /* Timer */ 64 #define CONFIG_MCFTMR 65 #undef CONFIG_MCFPIT 66 67 /* I2C */ 68 #define CONFIG_SYS_I2C 69 #define CONFIG_SYS_I2C_FSL 70 #define CONFIG_SYS_FSL_I2C_SPEED 80000 71 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 72 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 73 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 74 75 #define CONFIG_UDP_CHECKSUM 76 77 #ifdef CONFIG_MCFFEC 78 # define CONFIG_IPADDR 192.162.1.2 79 # define CONFIG_NETMASK 255.255.255.0 80 # define CONFIG_SERVERIP 192.162.1.1 81 # define CONFIG_GATEWAYIP 192.162.1.1 82 #endif /* FEC_ENET */ 83 84 #define CONFIG_HOSTNAME M53017 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 "netdev=eth0\0" \ 87 "loadaddr=40010000\0" \ 88 "u-boot=u-boot.bin\0" \ 89 "load=tftp ${loadaddr) ${u-boot}\0" \ 90 "upd=run load; run prog\0" \ 91 "prog=prot off 0 3ffff;" \ 92 "era 0 3ffff;" \ 93 "cp.b ${loadaddr} 0 ${filesize};" \ 94 "save\0" \ 95 "" 96 97 #define CONFIG_PRAM 512 /* 512 KB */ 98 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 99 100 #define CONFIG_SYS_LOAD_ADDR 0x40010000 101 102 #define CONFIG_SYS_CLK 80000000 103 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 104 105 #define CONFIG_SYS_MBAR 0xFC000000 106 107 /* 108 * Low Level Configuration Settings 109 * (address mappings, register initial values, etc.) 110 * You should know what you are doing if you make changes here. 111 */ 112 /* 113 * Definitions for initial stack pointer and data area (in DPRAM) 114 */ 115 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 116 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 117 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 118 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 119 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 120 121 /* 122 * Start addresses for the final memory configuration 123 * (Set up by the startup code) 124 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 125 */ 126 #define CONFIG_SYS_SDRAM_BASE 0x40000000 127 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 128 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 129 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 130 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 131 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 132 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 133 134 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 135 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 136 137 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 138 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 139 140 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 141 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 142 143 /* 144 * For booting Linux, the board info and command line data 145 * have to be in the first 8 MB of memory, since this is 146 * the maximum mapped by the Linux kernel during initialization ?? 147 */ 148 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 149 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 150 151 /*----------------------------------------------------------------------- 152 * FLASH organization 153 */ 154 #define CONFIG_SYS_FLASH_CFI 155 #ifdef CONFIG_SYS_FLASH_CFI 156 # define CONFIG_FLASH_CFI_DRIVER 1 157 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 158 # define CONFIG_FLASH_SPANSION_S29WS_N 1 159 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 160 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 161 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 162 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 163 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 164 #endif 165 166 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 167 168 /* Configuration for environment 169 * Environment is embedded in u-boot in the second sector of the flash 170 */ 171 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) 172 #define CONFIG_ENV_SIZE 0x1000 173 #define CONFIG_ENV_SECT_SIZE 0x8000 174 175 #define LDS_BOARD_TEXT \ 176 . = DEFINED(env_offset) ? env_offset : .; \ 177 env/embedded.o(.text*) 178 179 /*----------------------------------------------------------------------- 180 * Cache Configuration 181 */ 182 #define CONFIG_SYS_CACHELINE_SIZE 16 183 184 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 185 CONFIG_SYS_INIT_RAM_SIZE - 8) 186 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 187 CONFIG_SYS_INIT_RAM_SIZE - 4) 188 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 189 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 190 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 191 CF_ACR_EN | CF_ACR_SM_ALL) 192 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 193 CF_CACR_DCM_P) 194 195 /*----------------------------------------------------------------------- 196 * Chipselect bank definitions 197 */ 198 /* 199 * CS0 - NOR Flash 200 * CS1 - Ext SRAM 201 * CS2 - Available 202 * CS3 - Available 203 * CS4 - Available 204 * CS5 - Available 205 */ 206 #define CONFIG_SYS_CS0_BASE 0 207 #define CONFIG_SYS_CS0_MASK 0x00FF0001 208 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 209 210 #define CONFIG_SYS_CS1_BASE 0xC0000000 211 #define CONFIG_SYS_CS1_MASK 0x00070001 212 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 213 214 #endif /* _M53017EVB_H */ 215