1 /* 2 * Configuation settings for the Freescale MCF53017EVB. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M53017EVB_H 15 #define _M53017EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 27 28 #define CONFIG_SYS_UNIFY_CACHE 29 30 #define CONFIG_MCFFEC 31 #ifdef CONFIG_MCFFEC 32 # define CONFIG_MII 1 33 # define CONFIG_MII_INIT 1 34 # define CONFIG_SYS_DISCOVER_PHY 35 # define CONFIG_SYS_RX_ETH_BUFFER 8 36 # define CONFIG_SYS_TX_ETH_BUFFER 8 37 # define CONFIG_SYS_FEC_BUF_USE_SRAM 38 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 # define CONFIG_HAS_ETH1 40 41 # define CONFIG_SYS_FEC0_PINMUX 0 42 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 43 # define CONFIG_SYS_FEC1_PINMUX 0 44 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 45 # define MCFFEC_TOUT_LOOP 50000 46 47 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" 48 49 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 50 # ifndef CONFIG_SYS_DISCOVER_PHY 51 # define FECDUPLEX FULL 52 # define FECSPEED _100BASET 53 # else 54 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 # endif 57 # endif /* CONFIG_SYS_DISCOVER_PHY */ 58 #endif 59 60 #define CONFIG_MCFRTC 61 #undef RTC_DEBUG 62 #define CONFIG_SYS_RTC_CNT (0x8000) 63 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 64 65 /* Timer */ 66 #define CONFIG_MCFTMR 67 #undef CONFIG_MCFPIT 68 69 /* I2C */ 70 #define CONFIG_SYS_I2C 71 #define CONFIG_SYS_I2C_FSL 72 #define CONFIG_SYS_FSL_I2C_SPEED 80000 73 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 74 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 75 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 76 77 #define CONFIG_UDP_CHECKSUM 78 79 #ifdef CONFIG_MCFFEC 80 # define CONFIG_IPADDR 192.162.1.2 81 # define CONFIG_NETMASK 255.255.255.0 82 # define CONFIG_SERVERIP 192.162.1.1 83 # define CONFIG_GATEWAYIP 192.162.1.1 84 #endif /* FEC_ENET */ 85 86 #define CONFIG_HOSTNAME M53017 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 "netdev=eth0\0" \ 89 "loadaddr=40010000\0" \ 90 "u-boot=u-boot.bin\0" \ 91 "load=tftp ${loadaddr) ${u-boot}\0" \ 92 "upd=run load; run prog\0" \ 93 "prog=prot off 0 3ffff;" \ 94 "era 0 3ffff;" \ 95 "cp.b ${loadaddr} 0 ${filesize};" \ 96 "save\0" \ 97 "" 98 99 #define CONFIG_PRAM 512 /* 512 KB */ 100 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 101 102 #ifdef CONFIG_CMD_KGDB 103 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 104 #else 105 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 #endif 107 108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 109 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 111 #define CONFIG_SYS_LOAD_ADDR 0x40010000 112 113 #define CONFIG_SYS_CLK 80000000 114 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 115 116 #define CONFIG_SYS_MBAR 0xFC000000 117 118 /* 119 * Low Level Configuration Settings 120 * (address mappings, register initial values, etc.) 121 * You should know what you are doing if you make changes here. 122 */ 123 /* 124 * Definitions for initial stack pointer and data area (in DPRAM) 125 */ 126 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 127 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 128 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 129 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 130 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 131 132 /* 133 * Start addresses for the final memory configuration 134 * (Set up by the startup code) 135 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 136 */ 137 #define CONFIG_SYS_SDRAM_BASE 0x40000000 138 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 139 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 140 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 141 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 142 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 143 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 144 145 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 146 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 147 148 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 149 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 150 151 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 152 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 153 154 /* 155 * For booting Linux, the board info and command line data 156 * have to be in the first 8 MB of memory, since this is 157 * the maximum mapped by the Linux kernel during initialization ?? 158 */ 159 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 160 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 161 162 /*----------------------------------------------------------------------- 163 * FLASH organization 164 */ 165 #define CONFIG_SYS_FLASH_CFI 166 #ifdef CONFIG_SYS_FLASH_CFI 167 # define CONFIG_FLASH_CFI_DRIVER 1 168 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 169 # define CONFIG_FLASH_SPANSION_S29WS_N 1 170 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 171 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 172 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 173 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 174 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 175 #endif 176 177 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 178 179 /* Configuration for environment 180 * Environment is embedded in u-boot in the second sector of the flash 181 */ 182 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) 183 #define CONFIG_ENV_SIZE 0x1000 184 #define CONFIG_ENV_SECT_SIZE 0x8000 185 186 #define LDS_BOARD_TEXT \ 187 . = DEFINED(env_offset) ? env_offset : .; \ 188 common/env_embedded.o (.text*) 189 190 /*----------------------------------------------------------------------- 191 * Cache Configuration 192 */ 193 #define CONFIG_SYS_CACHELINE_SIZE 16 194 195 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 196 CONFIG_SYS_INIT_RAM_SIZE - 8) 197 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 198 CONFIG_SYS_INIT_RAM_SIZE - 4) 199 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 200 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 201 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 202 CF_ACR_EN | CF_ACR_SM_ALL) 203 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 204 CF_CACR_DCM_P) 205 206 /*----------------------------------------------------------------------- 207 * Chipselect bank definitions 208 */ 209 /* 210 * CS0 - NOR Flash 211 * CS1 - Ext SRAM 212 * CS2 - Available 213 * CS3 - Available 214 * CS4 - Available 215 * CS5 - Available 216 */ 217 #define CONFIG_SYS_CS0_BASE 0 218 #define CONFIG_SYS_CS0_MASK 0x00FF0001 219 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 220 221 #define CONFIG_SYS_CS1_BASE 0xC0000000 222 #define CONFIG_SYS_CS1_MASK 0x00070001 223 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 224 225 #endif /* _M53017EVB_H */ 226