1 /* 2 * Configuation settings for the Freescale MCF53017EVB. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M53017EVB_H 15 #define _M53017EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF5301x /* define processor family */ 22 #define CONFIG_M53015 /* define processor type */ 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 30 31 /* Command line configuration */ 32 #include <config_cmd_default.h> 33 34 #define CONFIG_CMD_CACHE 35 #define CONFIG_CMD_DATE 36 #define CONFIG_CMD_ELF 37 #define CONFIG_CMD_FLASH 38 #undef CONFIG_CMD_I2C 39 #define CONFIG_CMD_MEMORY 40 #define CONFIG_CMD_MISC 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_NET 43 #define CONFIG_CMD_PING 44 #define CONFIG_CMD_REGINFO 45 46 #define CONFIG_SYS_UNIFY_CACHE 47 48 #define CONFIG_MCFFEC 49 #ifdef CONFIG_MCFFEC 50 # define CONFIG_MII 1 51 # define CONFIG_MII_INIT 1 52 # define CONFIG_SYS_DISCOVER_PHY 53 # define CONFIG_SYS_RX_ETH_BUFFER 8 54 # define CONFIG_SYS_TX_ETH_BUFFER 8 55 # define CONFIG_SYS_FEC_BUF_USE_SRAM 56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 # define CONFIG_HAS_ETH1 58 59 # define CONFIG_SYS_FEC0_PINMUX 0 60 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 61 # define CONFIG_SYS_FEC1_PINMUX 0 62 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 63 # define MCFFEC_TOUT_LOOP 50000 64 65 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" 66 67 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 68 # ifndef CONFIG_SYS_DISCOVER_PHY 69 # define FECDUPLEX FULL 70 # define FECSPEED _100BASET 71 # else 72 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 73 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # endif 75 # endif /* CONFIG_SYS_DISCOVER_PHY */ 76 #endif 77 78 #define CONFIG_MCFRTC 79 #undef RTC_DEBUG 80 #define CONFIG_SYS_RTC_CNT (0x8000) 81 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 82 83 /* Timer */ 84 #define CONFIG_MCFTMR 85 #undef CONFIG_MCFPIT 86 87 /* I2C */ 88 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_I2C_FSL 90 #define CONFIG_SYS_FSL_I2C_SPEED 80000 91 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 92 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 93 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 94 95 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 96 #define CONFIG_UDP_CHECKSUM 97 98 #ifdef CONFIG_MCFFEC 99 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 100 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 101 # define CONFIG_IPADDR 192.162.1.2 102 # define CONFIG_NETMASK 255.255.255.0 103 # define CONFIG_SERVERIP 192.162.1.1 104 # define CONFIG_GATEWAYIP 192.162.1.1 105 # define CONFIG_OVERWRITE_ETHADDR_ONCE 106 #endif /* FEC_ENET */ 107 108 #define CONFIG_HOSTNAME M53017 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 "netdev=eth0\0" \ 111 "loadaddr=40010000\0" \ 112 "u-boot=u-boot.bin\0" \ 113 "load=tftp ${loadaddr) ${u-boot}\0" \ 114 "upd=run load; run prog\0" \ 115 "prog=prot off 0 3ffff;" \ 116 "era 0 3ffff;" \ 117 "cp.b ${loadaddr} 0 ${filesize};" \ 118 "save\0" \ 119 "" 120 121 #define CONFIG_PRAM 512 /* 512 KB */ 122 #define CONFIG_SYS_PROMPT "-> " 123 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 124 125 #ifdef CONFIG_CMD_KGDB 126 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 127 #else 128 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 129 #endif 130 131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 132 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 134 #define CONFIG_SYS_LOAD_ADDR 0x40010000 135 136 #define CONFIG_SYS_HZ 1000 137 #define CONFIG_SYS_CLK 80000000 138 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 139 140 #define CONFIG_SYS_MBAR 0xFC000000 141 142 /* 143 * Low Level Configuration Settings 144 * (address mappings, register initial values, etc.) 145 * You should know what you are doing if you make changes here. 146 */ 147 /* 148 * Definitions for initial stack pointer and data area (in DPRAM) 149 */ 150 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 152 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 153 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 154 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 155 156 /* 157 * Start addresses for the final memory configuration 158 * (Set up by the startup code) 159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 160 */ 161 #define CONFIG_SYS_SDRAM_BASE 0x40000000 162 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 163 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 164 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 165 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 166 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 167 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 168 169 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 170 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 171 172 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 173 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 174 175 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 176 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 177 178 /* 179 * For booting Linux, the board info and command line data 180 * have to be in the first 8 MB of memory, since this is 181 * the maximum mapped by the Linux kernel during initialization ?? 182 */ 183 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 184 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 185 186 /*----------------------------------------------------------------------- 187 * FLASH organization 188 */ 189 #define CONFIG_SYS_FLASH_CFI 190 #ifdef CONFIG_SYS_FLASH_CFI 191 # define CONFIG_FLASH_CFI_DRIVER 1 192 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 193 # define CONFIG_FLASH_SPANSION_S29WS_N 1 194 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 195 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 196 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 197 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 198 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 199 #endif 200 201 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 202 203 /* Configuration for environment 204 * Environment is embedded in u-boot in the second sector of the flash 205 */ 206 #define CONFIG_ENV_OFFSET 0x8000 207 #define CONFIG_ENV_SIZE 0x1000 208 #define CONFIG_ENV_SECT_SIZE 0x8000 209 #define CONFIG_ENV_IS_IN_FLASH 1 210 211 /*----------------------------------------------------------------------- 212 * Cache Configuration 213 */ 214 #define CONFIG_SYS_CACHELINE_SIZE 16 215 216 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 217 CONFIG_SYS_INIT_RAM_SIZE - 8) 218 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 219 CONFIG_SYS_INIT_RAM_SIZE - 4) 220 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 221 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 222 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 223 CF_ACR_EN | CF_ACR_SM_ALL) 224 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 225 CF_CACR_DCM_P) 226 227 /*----------------------------------------------------------------------- 228 * Chipselect bank definitions 229 */ 230 /* 231 * CS0 - NOR Flash 232 * CS1 - Ext SRAM 233 * CS2 - Available 234 * CS3 - Available 235 * CS4 - Available 236 * CS5 - Available 237 */ 238 #define CONFIG_SYS_CS0_BASE 0 239 #define CONFIG_SYS_CS0_MASK 0x00FF0001 240 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 241 242 #define CONFIG_SYS_CS1_BASE 0xC0000000 243 #define CONFIG_SYS_CS1_MASK 0x00070001 244 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 245 246 #endif /* _M53017EVB_H */ 247