1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF53017EVB. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M53017EVB_H 14 #define _M53017EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 5000 26 27 #define CONFIG_SYS_UNIFY_CACHE 28 29 #define CONFIG_MCFFEC 30 #ifdef CONFIG_MCFFEC 31 # define CONFIG_MII_INIT 1 32 # define CONFIG_SYS_DISCOVER_PHY 33 # define CONFIG_SYS_RX_ETH_BUFFER 8 34 # define CONFIG_SYS_TX_ETH_BUFFER 8 35 # define CONFIG_SYS_FEC_BUF_USE_SRAM 36 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 37 # define CONFIG_HAS_ETH1 38 39 # define CONFIG_SYS_FEC0_PINMUX 0 40 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 41 # define CONFIG_SYS_FEC1_PINMUX 0 42 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 43 # define MCFFEC_TOUT_LOOP 50000 44 45 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 46 # ifndef CONFIG_SYS_DISCOVER_PHY 47 # define FECDUPLEX FULL 48 # define FECSPEED _100BASET 49 # else 50 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52 # endif 53 # endif /* CONFIG_SYS_DISCOVER_PHY */ 54 #endif 55 56 #define CONFIG_MCFRTC 57 #undef RTC_DEBUG 58 #define CONFIG_SYS_RTC_CNT (0x8000) 59 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 60 61 /* Timer */ 62 #define CONFIG_MCFTMR 63 #undef CONFIG_MCFPIT 64 65 /* I2C */ 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_I2C_FSL 68 #define CONFIG_SYS_FSL_I2C_SPEED 80000 69 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 70 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 71 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 72 73 #define CONFIG_UDP_CHECKSUM 74 75 #ifdef CONFIG_MCFFEC 76 # define CONFIG_IPADDR 192.162.1.2 77 # define CONFIG_NETMASK 255.255.255.0 78 # define CONFIG_SERVERIP 192.162.1.1 79 # define CONFIG_GATEWAYIP 192.162.1.1 80 #endif /* FEC_ENET */ 81 82 #define CONFIG_HOSTNAME "M53017" 83 #define CONFIG_EXTRA_ENV_SETTINGS \ 84 "netdev=eth0\0" \ 85 "loadaddr=40010000\0" \ 86 "u-boot=u-boot.bin\0" \ 87 "load=tftp ${loadaddr) ${u-boot}\0" \ 88 "upd=run load; run prog\0" \ 89 "prog=prot off 0 3ffff;" \ 90 "era 0 3ffff;" \ 91 "cp.b ${loadaddr} 0 ${filesize};" \ 92 "save\0" \ 93 "" 94 95 #define CONFIG_PRAM 512 /* 512 KB */ 96 97 #define CONFIG_SYS_LOAD_ADDR 0x40010000 98 99 #define CONFIG_SYS_CLK 80000000 100 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 101 102 #define CONFIG_SYS_MBAR 0xFC000000 103 104 /* 105 * Low Level Configuration Settings 106 * (address mappings, register initial values, etc.) 107 * You should know what you are doing if you make changes here. 108 */ 109 /* 110 * Definitions for initial stack pointer and data area (in DPRAM) 111 */ 112 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 113 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 114 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 115 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 116 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 117 118 /* 119 * Start addresses for the final memory configuration 120 * (Set up by the startup code) 121 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 122 */ 123 #define CONFIG_SYS_SDRAM_BASE 0x40000000 124 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 125 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 126 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 127 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 128 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 129 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 130 131 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 132 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 133 134 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 135 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 136 137 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 138 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 139 140 /* 141 * For booting Linux, the board info and command line data 142 * have to be in the first 8 MB of memory, since this is 143 * the maximum mapped by the Linux kernel during initialization ?? 144 */ 145 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 146 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 147 148 /*----------------------------------------------------------------------- 149 * FLASH organization 150 */ 151 #ifdef CONFIG_SYS_FLASH_CFI 152 # define CONFIG_FLASH_SPANSION_S29WS_N 1 153 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 154 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 155 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 156 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 157 #endif 158 159 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 160 161 /* Configuration for environment 162 * Environment is embedded in u-boot in the second sector of the flash 163 */ 164 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) 165 #define CONFIG_ENV_SIZE 0x1000 166 #define CONFIG_ENV_SECT_SIZE 0x8000 167 168 #define LDS_BOARD_TEXT \ 169 . = DEFINED(env_offset) ? env_offset : .; \ 170 env/embedded.o(.text*) 171 172 /*----------------------------------------------------------------------- 173 * Cache Configuration 174 */ 175 #define CONFIG_SYS_CACHELINE_SIZE 16 176 177 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 178 CONFIG_SYS_INIT_RAM_SIZE - 8) 179 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 180 CONFIG_SYS_INIT_RAM_SIZE - 4) 181 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 182 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 183 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 184 CF_ACR_EN | CF_ACR_SM_ALL) 185 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 186 CF_CACR_DCM_P) 187 188 /*----------------------------------------------------------------------- 189 * Chipselect bank definitions 190 */ 191 /* 192 * CS0 - NOR Flash 193 * CS1 - Ext SRAM 194 * CS2 - Available 195 * CS3 - Available 196 * CS4 - Available 197 * CS5 - Available 198 */ 199 #define CONFIG_SYS_CS0_BASE 0 200 #define CONFIG_SYS_CS0_MASK 0x00FF0001 201 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 202 203 #define CONFIG_SYS_CS1_BASE 0xC0000000 204 #define CONFIG_SYS_CS1_MASK 0x00070001 205 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 206 207 #endif /* _M53017EVB_H */ 208