1 /* 2 * Configuation settings for the Freescale MCF53017EVB. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M53017EVB_H 15 #define _M53017EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 28 29 /* Command line configuration */ 30 #define CONFIG_CMD_CACHE 31 #define CONFIG_CMD_DATE 32 #define CONFIG_CMD_ELF 33 #undef CONFIG_CMD_I2C 34 #define CONFIG_CMD_MII 35 #define CONFIG_CMD_PING 36 #define CONFIG_CMD_REGINFO 37 38 #define CONFIG_SYS_UNIFY_CACHE 39 40 #define CONFIG_MCFFEC 41 #ifdef CONFIG_MCFFEC 42 # define CONFIG_MII 1 43 # define CONFIG_MII_INIT 1 44 # define CONFIG_SYS_DISCOVER_PHY 45 # define CONFIG_SYS_RX_ETH_BUFFER 8 46 # define CONFIG_SYS_TX_ETH_BUFFER 8 47 # define CONFIG_SYS_FEC_BUF_USE_SRAM 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 # define CONFIG_HAS_ETH1 50 51 # define CONFIG_SYS_FEC0_PINMUX 0 52 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 53 # define CONFIG_SYS_FEC1_PINMUX 0 54 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 55 # define MCFFEC_TOUT_LOOP 50000 56 57 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" 58 59 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 60 # ifndef CONFIG_SYS_DISCOVER_PHY 61 # define FECDUPLEX FULL 62 # define FECSPEED _100BASET 63 # else 64 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 65 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # endif 67 # endif /* CONFIG_SYS_DISCOVER_PHY */ 68 #endif 69 70 #define CONFIG_MCFRTC 71 #undef RTC_DEBUG 72 #define CONFIG_SYS_RTC_CNT (0x8000) 73 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 74 75 /* Timer */ 76 #define CONFIG_MCFTMR 77 #undef CONFIG_MCFPIT 78 79 /* I2C */ 80 #define CONFIG_SYS_I2C 81 #define CONFIG_SYS_I2C_FSL 82 #define CONFIG_SYS_FSL_I2C_SPEED 80000 83 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 84 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 85 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 86 87 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 88 #define CONFIG_UDP_CHECKSUM 89 90 #ifdef CONFIG_MCFFEC 91 # define CONFIG_IPADDR 192.162.1.2 92 # define CONFIG_NETMASK 255.255.255.0 93 # define CONFIG_SERVERIP 192.162.1.1 94 # define CONFIG_GATEWAYIP 192.162.1.1 95 #endif /* FEC_ENET */ 96 97 #define CONFIG_HOSTNAME M53017 98 #define CONFIG_EXTRA_ENV_SETTINGS \ 99 "netdev=eth0\0" \ 100 "loadaddr=40010000\0" \ 101 "u-boot=u-boot.bin\0" \ 102 "load=tftp ${loadaddr) ${u-boot}\0" \ 103 "upd=run load; run prog\0" \ 104 "prog=prot off 0 3ffff;" \ 105 "era 0 3ffff;" \ 106 "cp.b ${loadaddr} 0 ${filesize};" \ 107 "save\0" \ 108 "" 109 110 #define CONFIG_PRAM 512 /* 512 KB */ 111 #define CONFIG_SYS_PROMPT "-> " 112 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 113 114 #ifdef CONFIG_CMD_KGDB 115 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 116 #else 117 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 118 #endif 119 120 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 121 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 122 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 123 #define CONFIG_SYS_LOAD_ADDR 0x40010000 124 125 #define CONFIG_SYS_CLK 80000000 126 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 127 128 #define CONFIG_SYS_MBAR 0xFC000000 129 130 /* 131 * Low Level Configuration Settings 132 * (address mappings, register initial values, etc.) 133 * You should know what you are doing if you make changes here. 134 */ 135 /* 136 * Definitions for initial stack pointer and data area (in DPRAM) 137 */ 138 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 139 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 140 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 141 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 142 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 143 144 /* 145 * Start addresses for the final memory configuration 146 * (Set up by the startup code) 147 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 148 */ 149 #define CONFIG_SYS_SDRAM_BASE 0x40000000 150 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 151 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 152 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 153 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 154 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 155 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 156 157 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 158 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 159 160 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 161 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 162 163 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 164 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 165 166 /* 167 * For booting Linux, the board info and command line data 168 * have to be in the first 8 MB of memory, since this is 169 * the maximum mapped by the Linux kernel during initialization ?? 170 */ 171 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 172 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 173 174 /*----------------------------------------------------------------------- 175 * FLASH organization 176 */ 177 #define CONFIG_SYS_FLASH_CFI 178 #ifdef CONFIG_SYS_FLASH_CFI 179 # define CONFIG_FLASH_CFI_DRIVER 1 180 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 181 # define CONFIG_FLASH_SPANSION_S29WS_N 1 182 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 183 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 184 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 185 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 186 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 187 #endif 188 189 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 190 191 /* Configuration for environment 192 * Environment is embedded in u-boot in the second sector of the flash 193 */ 194 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) 195 #define CONFIG_ENV_SIZE 0x1000 196 #define CONFIG_ENV_SECT_SIZE 0x8000 197 #define CONFIG_ENV_IS_IN_FLASH 1 198 199 #define LDS_BOARD_TEXT \ 200 . = DEFINED(env_offset) ? env_offset : .; \ 201 common/env_embedded.o (.text*) 202 203 /*----------------------------------------------------------------------- 204 * Cache Configuration 205 */ 206 #define CONFIG_SYS_CACHELINE_SIZE 16 207 208 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - 8) 210 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 211 CONFIG_SYS_INIT_RAM_SIZE - 4) 212 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 213 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 214 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 215 CF_ACR_EN | CF_ACR_SM_ALL) 216 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 217 CF_CACR_DCM_P) 218 219 /*----------------------------------------------------------------------- 220 * Chipselect bank definitions 221 */ 222 /* 223 * CS0 - NOR Flash 224 * CS1 - Ext SRAM 225 * CS2 - Available 226 * CS3 - Available 227 * CS4 - Available 228 * CS5 - Available 229 */ 230 #define CONFIG_SYS_CS0_BASE 0 231 #define CONFIG_SYS_CS0_MASK 0x00FF0001 232 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 233 234 #define CONFIG_SYS_CS1_BASE 0xC0000000 235 #define CONFIG_SYS_CS1_MASK 0x00070001 236 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 237 238 #endif /* _M53017EVB_H */ 239