1 /* 2 * Configuation settings for the Freescale MCF53017EVB. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M53017EVB_H 15 #define _M53017EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 27 28 /* Command line configuration */ 29 #define CONFIG_CMD_DATE 30 #define CONFIG_CMD_REGINFO 31 32 #define CONFIG_SYS_UNIFY_CACHE 33 34 #define CONFIG_MCFFEC 35 #ifdef CONFIG_MCFFEC 36 # define CONFIG_MII 1 37 # define CONFIG_MII_INIT 1 38 # define CONFIG_SYS_DISCOVER_PHY 39 # define CONFIG_SYS_RX_ETH_BUFFER 8 40 # define CONFIG_SYS_TX_ETH_BUFFER 8 41 # define CONFIG_SYS_FEC_BUF_USE_SRAM 42 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43 # define CONFIG_HAS_ETH1 44 45 # define CONFIG_SYS_FEC0_PINMUX 0 46 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 47 # define CONFIG_SYS_FEC1_PINMUX 0 48 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 49 # define MCFFEC_TOUT_LOOP 50000 50 51 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" 52 53 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 54 # ifndef CONFIG_SYS_DISCOVER_PHY 55 # define FECDUPLEX FULL 56 # define FECSPEED _100BASET 57 # else 58 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # endif 61 # endif /* CONFIG_SYS_DISCOVER_PHY */ 62 #endif 63 64 #define CONFIG_MCFRTC 65 #undef RTC_DEBUG 66 #define CONFIG_SYS_RTC_CNT (0x8000) 67 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) 68 69 /* Timer */ 70 #define CONFIG_MCFTMR 71 #undef CONFIG_MCFPIT 72 73 /* I2C */ 74 #define CONFIG_SYS_I2C 75 #define CONFIG_SYS_I2C_FSL 76 #define CONFIG_SYS_FSL_I2C_SPEED 80000 77 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 78 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 79 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 80 81 #define CONFIG_UDP_CHECKSUM 82 83 #ifdef CONFIG_MCFFEC 84 # define CONFIG_IPADDR 192.162.1.2 85 # define CONFIG_NETMASK 255.255.255.0 86 # define CONFIG_SERVERIP 192.162.1.1 87 # define CONFIG_GATEWAYIP 192.162.1.1 88 #endif /* FEC_ENET */ 89 90 #define CONFIG_HOSTNAME M53017 91 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 "netdev=eth0\0" \ 93 "loadaddr=40010000\0" \ 94 "u-boot=u-boot.bin\0" \ 95 "load=tftp ${loadaddr) ${u-boot}\0" \ 96 "upd=run load; run prog\0" \ 97 "prog=prot off 0 3ffff;" \ 98 "era 0 3ffff;" \ 99 "cp.b ${loadaddr} 0 ${filesize};" \ 100 "save\0" \ 101 "" 102 103 #define CONFIG_PRAM 512 /* 512 KB */ 104 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 106 #ifdef CONFIG_CMD_KGDB 107 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 108 #else 109 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 110 #endif 111 112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 115 #define CONFIG_SYS_LOAD_ADDR 0x40010000 116 117 #define CONFIG_SYS_CLK 80000000 118 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 119 120 #define CONFIG_SYS_MBAR 0xFC000000 121 122 /* 123 * Low Level Configuration Settings 124 * (address mappings, register initial values, etc.) 125 * You should know what you are doing if you make changes here. 126 */ 127 /* 128 * Definitions for initial stack pointer and data area (in DPRAM) 129 */ 130 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 131 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ 132 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 133 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 135 136 /* 137 * Start addresses for the final memory configuration 138 * (Set up by the startup code) 139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 140 */ 141 #define CONFIG_SYS_SDRAM_BASE 0x40000000 142 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 143 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 144 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 145 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 146 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 147 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 148 149 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 150 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 151 152 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 153 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 154 155 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 156 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 157 158 /* 159 * For booting Linux, the board info and command line data 160 * have to be in the first 8 MB of memory, since this is 161 * the maximum mapped by the Linux kernel during initialization ?? 162 */ 163 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 164 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 165 166 /*----------------------------------------------------------------------- 167 * FLASH organization 168 */ 169 #define CONFIG_SYS_FLASH_CFI 170 #ifdef CONFIG_SYS_FLASH_CFI 171 # define CONFIG_FLASH_CFI_DRIVER 1 172 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 173 # define CONFIG_FLASH_SPANSION_S29WS_N 1 174 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 175 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 176 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 178 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 179 #endif 180 181 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 182 183 /* Configuration for environment 184 * Environment is embedded in u-boot in the second sector of the flash 185 */ 186 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) 187 #define CONFIG_ENV_SIZE 0x1000 188 #define CONFIG_ENV_SECT_SIZE 0x8000 189 #define CONFIG_ENV_IS_IN_FLASH 1 190 191 #define LDS_BOARD_TEXT \ 192 . = DEFINED(env_offset) ? env_offset : .; \ 193 common/env_embedded.o (.text*) 194 195 /*----------------------------------------------------------------------- 196 * Cache Configuration 197 */ 198 #define CONFIG_SYS_CACHELINE_SIZE 16 199 200 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 201 CONFIG_SYS_INIT_RAM_SIZE - 8) 202 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 203 CONFIG_SYS_INIT_RAM_SIZE - 4) 204 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 205 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 206 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 207 CF_ACR_EN | CF_ACR_SM_ALL) 208 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 209 CF_CACR_DCM_P) 210 211 /*----------------------------------------------------------------------- 212 * Chipselect bank definitions 213 */ 214 /* 215 * CS0 - NOR Flash 216 * CS1 - Ext SRAM 217 * CS2 - Available 218 * CS3 - Available 219 * CS4 - Available 220 * CS5 - Available 221 */ 222 #define CONFIG_SYS_CS0_BASE 0 223 #define CONFIG_SYS_CS0_MASK 0x00FF0001 224 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 225 226 #define CONFIG_SYS_CS1_BASE 0xC0000000 227 #define CONFIG_SYS_CS1_MASK 0x00070001 228 #define CONFIG_SYS_CS1_CTRL 0x00001FA0 229 230 #endif /* _M53017EVB_H */ 231