1 /* 2 * Configuation settings for the Motorola MC5282EVB board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _CONFIG_M5282EVB_H 14 #define _CONFIG_M5282EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 26 27 /* Configuration for environment 28 * Environment is embedded in u-boot in the second sector of the flash 29 */ 30 #define CONFIG_ENV_ADDR 0xffe04000 31 #define CONFIG_ENV_SIZE 0x2000 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 env/embedded.o(.text*); 36 37 /* 38 * BOOTP options 39 */ 40 #define CONFIG_BOOTP_BOOTFILESIZE 41 42 /* 43 * Command line configuration. 44 */ 45 46 #define CONFIG_MCFFEC 47 #ifdef CONFIG_MCFFEC 48 # define CONFIG_MII 1 49 # define CONFIG_MII_INIT 1 50 # define CONFIG_SYS_DISCOVER_PHY 51 # define CONFIG_SYS_RX_ETH_BUFFER 8 52 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 54 # define CONFIG_SYS_FEC0_PINMUX 0 55 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 56 # define MCFFEC_TOUT_LOOP 50000 57 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 58 # ifndef CONFIG_SYS_DISCOVER_PHY 59 # define FECDUPLEX FULL 60 # define FECSPEED _100BASET 61 # else 62 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 # endif 65 # endif /* CONFIG_SYS_DISCOVER_PHY */ 66 #endif 67 68 #ifdef CONFIG_MCFFEC 69 # define CONFIG_IPADDR 192.162.1.2 70 # define CONFIG_NETMASK 255.255.255.0 71 # define CONFIG_SERVERIP 192.162.1.1 72 # define CONFIG_GATEWAYIP 192.162.1.1 73 #endif /* CONFIG_MCFFEC */ 74 75 #define CONFIG_HOSTNAME M5282EVB 76 #define CONFIG_EXTRA_ENV_SETTINGS \ 77 "netdev=eth0\0" \ 78 "loadaddr=10000\0" \ 79 "u-boot=u-boot.bin\0" \ 80 "load=tftp ${loadaddr) ${u-boot}\0" \ 81 "upd=run load; run prog\0" \ 82 "prog=prot off ffe00000 ffe3ffff;" \ 83 "era ffe00000 ffe3ffff;" \ 84 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 85 "save\0" \ 86 "" 87 88 #define CONFIG_SYS_LOAD_ADDR 0x20000 89 90 #define CONFIG_SYS_MEMTEST_START 0x400 91 #define CONFIG_SYS_MEMTEST_END 0x380000 92 93 #define CONFIG_SYS_CLK 64000000 94 95 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 96 97 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 98 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 99 100 /* 101 * Low Level Configuration Settings 102 * (address mappings, register initial values, etc.) 103 * You should know what you are doing if you make changes here. 104 */ 105 #define CONFIG_SYS_MBAR 0x40000000 106 107 /*----------------------------------------------------------------------- 108 * Definitions for initial stack pointer and data area (in DPRAM) 109 */ 110 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 111 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 112 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 114 115 /*----------------------------------------------------------------------- 116 * Start addresses for the final memory configuration 117 * (Set up by the startup code) 118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 119 */ 120 #define CONFIG_SYS_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 122 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 123 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 124 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 125 126 /* If M5282 port is fully implemented the monitor base will be behind 127 * the vector table. */ 128 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 129 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 130 #else 131 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 132 #endif 133 134 #define CONFIG_SYS_MONITOR_LEN 0x20000 135 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 136 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 137 138 /* 139 * For booting Linux, the board info and command line data 140 * have to be in the first 8 MB of memory, since this is 141 * the maximum mapped by the Linux kernel during initialization ?? 142 */ 143 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 144 145 /*----------------------------------------------------------------------- 146 * FLASH organization 147 */ 148 #define CONFIG_SYS_FLASH_CFI 149 #ifdef CONFIG_SYS_FLASH_CFI 150 151 # define CONFIG_FLASH_CFI_DRIVER 1 152 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 153 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 154 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 155 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 156 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 157 # define CONFIG_SYS_FLASH_CHECKSUM 158 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 159 #endif 160 161 /*----------------------------------------------------------------------- 162 * Cache Configuration 163 */ 164 #define CONFIG_SYS_CACHELINE_SIZE 16 165 166 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 167 CONFIG_SYS_INIT_RAM_SIZE - 8) 168 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 169 CONFIG_SYS_INIT_RAM_SIZE - 4) 170 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 171 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 172 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 173 CF_ACR_EN | CF_ACR_SM_ALL) 174 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 175 CF_CACR_CEIB | CF_CACR_DBWE | \ 176 CF_CACR_EUSP) 177 178 /*----------------------------------------------------------------------- 179 * Memory bank definitions 180 */ 181 #define CONFIG_SYS_CS0_BASE 0xFFE00000 182 #define CONFIG_SYS_CS0_CTRL 0x00001980 183 #define CONFIG_SYS_CS0_MASK 0x001F0001 184 185 /*----------------------------------------------------------------------- 186 * Port configuration 187 */ 188 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 189 #define CONFIG_SYS_PADDR 0x0000000 190 #define CONFIG_SYS_PADAT 0x0000000 191 192 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 193 #define CONFIG_SYS_PBDDR 0x0000000 194 #define CONFIG_SYS_PBDAT 0x0000000 195 196 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 197 #define CONFIG_SYS_PCDDR 0x0000000 198 #define CONFIG_SYS_PCDAT 0x0000000 199 200 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 201 #define CONFIG_SYS_PCDDR 0x0000000 202 #define CONFIG_SYS_PCDAT 0x0000000 203 204 #define CONFIG_SYS_PEHLPAR 0xC0 205 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 206 #define CONFIG_SYS_DDRUA 0x05 207 #define CONFIG_SYS_PJPAR 0xFF 208 209 #endif /* _CONFIG_M5282EVB_H */ 210