1 /* 2 * Configuation settings for the Motorola MC5282EVB board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * board/config.h - configuration options, board specific 27 */ 28 29 #ifndef _CONFIG_M5282EVB_H 30 #define _CONFIG_M5282EVB_H 31 32 /* 33 * High Level Configuration Options 34 * (easy to change) 35 */ 36 #define CONFIG_MCF52x2 /* define processor family */ 37 #define CONFIG_M5282 /* define processor type */ 38 39 #define CONFIG_MCFTMR 40 41 #define CONFIG_MCFUART 42 #define CONFIG_SYS_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 47 48 /* Configuration for environment 49 * Environment is embedded in u-boot in the second sector of the flash 50 */ 51 #define CONFIG_ENV_ADDR 0xffe04000 52 #define CONFIG_ENV_SIZE 0x2000 53 #define CONFIG_ENV_IS_IN_FLASH 1 54 55 /* 56 * BOOTP options 57 */ 58 #define CONFIG_BOOTP_BOOTFILESIZE 59 #define CONFIG_BOOTP_BOOTPATH 60 #define CONFIG_BOOTP_GATEWAY 61 #define CONFIG_BOOTP_HOSTNAME 62 63 /* 64 * Command line configuration. 65 */ 66 #include <config_cmd_default.h> 67 #define CONFIG_CMD_CACHE 68 #define CONFIG_CMD_NET 69 #define CONFIG_CMD_PING 70 #define CONFIG_CMD_MII 71 72 #undef CONFIG_CMD_LOADS 73 #undef CONFIG_CMD_LOADB 74 75 #define CONFIG_MCFFEC 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_NET_MULTI 1 78 # define CONFIG_MII 1 79 # define CONFIG_MII_INIT 1 80 # define CONFIG_SYS_DISCOVER_PHY 81 # define CONFIG_SYS_RX_ETH_BUFFER 8 82 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 83 84 # define CONFIG_SYS_FEC0_PINMUX 0 85 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 86 # define MCFFEC_TOUT_LOOP 50000 87 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 88 # ifndef CONFIG_SYS_DISCOVER_PHY 89 # define FECDUPLEX FULL 90 # define FECSPEED _100BASET 91 # else 92 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 93 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 94 # endif 95 # endif /* CONFIG_SYS_DISCOVER_PHY */ 96 #endif 97 98 #define CONFIG_BOOTDELAY 5 99 #ifdef CONFIG_MCFFEC 100 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 101 # define CONFIG_IPADDR 192.162.1.2 102 # define CONFIG_NETMASK 255.255.255.0 103 # define CONFIG_SERVERIP 192.162.1.1 104 # define CONFIG_GATEWAYIP 192.162.1.1 105 # define CONFIG_OVERWRITE_ETHADDR_ONCE 106 #endif /* CONFIG_MCFFEC */ 107 108 #define CONFIG_HOSTNAME M5282EVB 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 "netdev=eth0\0" \ 111 "loadaddr=10000\0" \ 112 "u-boot=u-boot.bin\0" \ 113 "load=tftp ${loadaddr) ${u-boot}\0" \ 114 "upd=run load; run prog\0" \ 115 "prog=prot off ffe00000 ffe3ffff;" \ 116 "era ffe00000 ffe3ffff;" \ 117 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 118 "save\0" \ 119 "" 120 121 #define CONFIG_SYS_PROMPT "-> " 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 124 #if defined(CONFIG_CMD_KGDB) 125 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126 #else 127 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 128 #endif 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 133 #define CONFIG_SYS_LOAD_ADDR 0x20000 134 135 #define CONFIG_SYS_MEMTEST_START 0x400 136 #define CONFIG_SYS_MEMTEST_END 0x380000 137 138 #define CONFIG_SYS_HZ 1000 139 #define CONFIG_SYS_CLK 64000000 140 141 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 142 143 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 144 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 145 146 /* 147 * Low Level Configuration Settings 148 * (address mappings, register initial values, etc.) 149 * You should know what you are doing if you make changes here. 150 */ 151 #define CONFIG_SYS_MBAR 0x40000000 152 153 /*----------------------------------------------------------------------- 154 * Definitions for initial stack pointer and data area (in DPRAM) 155 */ 156 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 157 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 158 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 161 /*----------------------------------------------------------------------- 162 * Start addresses for the final memory configuration 163 * (Set up by the startup code) 164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 165 */ 166 #define CONFIG_SYS_SDRAM_BASE 0x00000000 167 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 168 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 169 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 170 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 171 172 /* If M5282 port is fully implemented the monitor base will be behind 173 * the vector table. */ 174 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 175 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 176 #else 177 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 178 #endif 179 180 #define CONFIG_SYS_MONITOR_LEN 0x20000 181 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 182 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 183 184 /* 185 * For booting Linux, the board info and command line data 186 * have to be in the first 8 MB of memory, since this is 187 * the maximum mapped by the Linux kernel during initialization ?? 188 */ 189 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 190 191 /*----------------------------------------------------------------------- 192 * FLASH organization 193 */ 194 #define CONFIG_SYS_FLASH_CFI 195 #ifdef CONFIG_SYS_FLASH_CFI 196 197 # define CONFIG_FLASH_CFI_DRIVER 1 198 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 199 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 200 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 201 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 202 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 203 # define CONFIG_SYS_FLASH_CHECKSUM 204 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 205 #endif 206 207 /*----------------------------------------------------------------------- 208 * Cache Configuration 209 */ 210 #define CONFIG_SYS_CACHELINE_SIZE 16 211 212 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 213 CONFIG_SYS_INIT_RAM_SIZE - 8) 214 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 215 CONFIG_SYS_INIT_RAM_SIZE - 4) 216 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 217 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 218 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 219 CF_ACR_EN | CF_ACR_SM_ALL) 220 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 221 CF_CACR_CEIB | CF_CACR_DBWE | \ 222 CF_CACR_EUSP) 223 224 /*----------------------------------------------------------------------- 225 * Memory bank definitions 226 */ 227 #define CONFIG_SYS_CS0_BASE 0xFFE00000 228 #define CONFIG_SYS_CS0_CTRL 0x00001980 229 #define CONFIG_SYS_CS0_MASK 0x001F0001 230 231 /*----------------------------------------------------------------------- 232 * Port configuration 233 */ 234 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 235 #define CONFIG_SYS_PADDR 0x0000000 236 #define CONFIG_SYS_PADAT 0x0000000 237 238 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 239 #define CONFIG_SYS_PBDDR 0x0000000 240 #define CONFIG_SYS_PBDAT 0x0000000 241 242 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 243 #define CONFIG_SYS_PCDDR 0x0000000 244 #define CONFIG_SYS_PCDAT 0x0000000 245 246 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 247 #define CONFIG_SYS_PCDDR 0x0000000 248 #define CONFIG_SYS_PCDAT 0x0000000 249 250 #define CONFIG_SYS_PEHLPAR 0xC0 251 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 252 #define CONFIG_SYS_DDRUA 0x05 253 #define CONFIG_SYS_PJPAR 0xFF 254 255 #endif /* _CONFIG_M5282EVB_H */ 256