1 /* 2 * Configuation settings for the Motorola MC5282EVB board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _CONFIG_M5282EVB_H 14 #define _CONFIG_M5282EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 27 28 /* Configuration for environment 29 * Environment is embedded in u-boot in the second sector of the flash 30 */ 31 #define CONFIG_ENV_ADDR 0xffe04000 32 #define CONFIG_ENV_SIZE 0x2000 33 #define CONFIG_ENV_IS_IN_FLASH 1 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text*); 38 39 /* 40 * BOOTP options 41 */ 42 #define CONFIG_BOOTP_BOOTFILESIZE 43 #define CONFIG_BOOTP_BOOTPATH 44 #define CONFIG_BOOTP_GATEWAY 45 #define CONFIG_BOOTP_HOSTNAME 46 47 /* 48 * Command line configuration. 49 */ 50 #include <config_cmd_default.h> 51 #define CONFIG_CMD_CACHE 52 #define CONFIG_CMD_PING 53 #define CONFIG_CMD_MII 54 55 #undef CONFIG_CMD_LOADS 56 #undef CONFIG_CMD_LOADB 57 58 #define CONFIG_MCFFEC 59 #ifdef CONFIG_MCFFEC 60 # define CONFIG_MII 1 61 # define CONFIG_MII_INIT 1 62 # define CONFIG_SYS_DISCOVER_PHY 63 # define CONFIG_SYS_RX_ETH_BUFFER 8 64 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 65 66 # define CONFIG_SYS_FEC0_PINMUX 0 67 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 68 # define MCFFEC_TOUT_LOOP 50000 69 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 70 # ifndef CONFIG_SYS_DISCOVER_PHY 71 # define FECDUPLEX FULL 72 # define FECSPEED _100BASET 73 # else 74 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 # endif 77 # endif /* CONFIG_SYS_DISCOVER_PHY */ 78 #endif 79 80 #define CONFIG_BOOTDELAY 5 81 #ifdef CONFIG_MCFFEC 82 # define CONFIG_IPADDR 192.162.1.2 83 # define CONFIG_NETMASK 255.255.255.0 84 # define CONFIG_SERVERIP 192.162.1.1 85 # define CONFIG_GATEWAYIP 192.162.1.1 86 #endif /* CONFIG_MCFFEC */ 87 88 #define CONFIG_HOSTNAME M5282EVB 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "netdev=eth0\0" \ 91 "loadaddr=10000\0" \ 92 "u-boot=u-boot.bin\0" \ 93 "load=tftp ${loadaddr) ${u-boot}\0" \ 94 "upd=run load; run prog\0" \ 95 "prog=prot off ffe00000 ffe3ffff;" \ 96 "era ffe00000 ffe3ffff;" \ 97 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 98 "save\0" \ 99 "" 100 101 #define CONFIG_SYS_PROMPT "-> " 102 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 103 104 #if defined(CONFIG_CMD_KGDB) 105 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 106 #else 107 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 108 #endif 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 112 113 #define CONFIG_SYS_LOAD_ADDR 0x20000 114 115 #define CONFIG_SYS_MEMTEST_START 0x400 116 #define CONFIG_SYS_MEMTEST_END 0x380000 117 118 #define CONFIG_SYS_CLK 64000000 119 120 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 121 122 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 123 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 124 125 /* 126 * Low Level Configuration Settings 127 * (address mappings, register initial values, etc.) 128 * You should know what you are doing if you make changes here. 129 */ 130 #define CONFIG_SYS_MBAR 0x40000000 131 132 /*----------------------------------------------------------------------- 133 * Definitions for initial stack pointer and data area (in DPRAM) 134 */ 135 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 136 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 137 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 138 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 139 140 /*----------------------------------------------------------------------- 141 * Start addresses for the final memory configuration 142 * (Set up by the startup code) 143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 144 */ 145 #define CONFIG_SYS_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 147 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 148 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 149 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 150 151 /* If M5282 port is fully implemented the monitor base will be behind 152 * the vector table. */ 153 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 154 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 155 #else 156 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 157 #endif 158 159 #define CONFIG_SYS_MONITOR_LEN 0x20000 160 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 161 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 162 163 /* 164 * For booting Linux, the board info and command line data 165 * have to be in the first 8 MB of memory, since this is 166 * the maximum mapped by the Linux kernel during initialization ?? 167 */ 168 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 169 170 /*----------------------------------------------------------------------- 171 * FLASH organization 172 */ 173 #define CONFIG_SYS_FLASH_CFI 174 #ifdef CONFIG_SYS_FLASH_CFI 175 176 # define CONFIG_FLASH_CFI_DRIVER 1 177 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 178 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 179 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 180 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 181 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 182 # define CONFIG_SYS_FLASH_CHECKSUM 183 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 184 #endif 185 186 /*----------------------------------------------------------------------- 187 * Cache Configuration 188 */ 189 #define CONFIG_SYS_CACHELINE_SIZE 16 190 191 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 192 CONFIG_SYS_INIT_RAM_SIZE - 8) 193 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 194 CONFIG_SYS_INIT_RAM_SIZE - 4) 195 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 196 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 197 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 198 CF_ACR_EN | CF_ACR_SM_ALL) 199 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 200 CF_CACR_CEIB | CF_CACR_DBWE | \ 201 CF_CACR_EUSP) 202 203 /*----------------------------------------------------------------------- 204 * Memory bank definitions 205 */ 206 #define CONFIG_SYS_CS0_BASE 0xFFE00000 207 #define CONFIG_SYS_CS0_CTRL 0x00001980 208 #define CONFIG_SYS_CS0_MASK 0x001F0001 209 210 /*----------------------------------------------------------------------- 211 * Port configuration 212 */ 213 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 214 #define CONFIG_SYS_PADDR 0x0000000 215 #define CONFIG_SYS_PADAT 0x0000000 216 217 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 218 #define CONFIG_SYS_PBDDR 0x0000000 219 #define CONFIG_SYS_PBDAT 0x0000000 220 221 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 222 #define CONFIG_SYS_PCDDR 0x0000000 223 #define CONFIG_SYS_PCDAT 0x0000000 224 225 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 226 #define CONFIG_SYS_PCDDR 0x0000000 227 #define CONFIG_SYS_PCDAT 0x0000000 228 229 #define CONFIG_SYS_PEHLPAR 0xC0 230 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 231 #define CONFIG_SYS_DDRUA 0x05 232 #define CONFIG_SYS_PJPAR 0xFF 233 234 #endif /* _CONFIG_M5282EVB_H */ 235