1 /* 2 * Configuation settings for the Motorola MC5282EVB board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _CONFIG_M5282EVB_H 14 #define _CONFIG_M5282EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 26 27 /* Configuration for environment 28 * Environment is embedded in u-boot in the second sector of the flash 29 */ 30 #define CONFIG_ENV_ADDR 0xffe04000 31 #define CONFIG_ENV_SIZE 0x2000 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 env/embedded.o(.text*); 36 37 /* 38 * BOOTP options 39 */ 40 #define CONFIG_BOOTP_BOOTFILESIZE 41 #define CONFIG_BOOTP_BOOTPATH 42 #define CONFIG_BOOTP_GATEWAY 43 #define CONFIG_BOOTP_HOSTNAME 44 45 /* 46 * Command line configuration. 47 */ 48 49 #define CONFIG_MCFFEC 50 #ifdef CONFIG_MCFFEC 51 # define CONFIG_MII 1 52 # define CONFIG_MII_INIT 1 53 # define CONFIG_SYS_DISCOVER_PHY 54 # define CONFIG_SYS_RX_ETH_BUFFER 8 55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 57 # define CONFIG_SYS_FEC0_PINMUX 0 58 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 # define MCFFEC_TOUT_LOOP 50000 60 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 61 # ifndef CONFIG_SYS_DISCOVER_PHY 62 # define FECDUPLEX FULL 63 # define FECSPEED _100BASET 64 # else 65 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # endif 68 # endif /* CONFIG_SYS_DISCOVER_PHY */ 69 #endif 70 71 #ifdef CONFIG_MCFFEC 72 # define CONFIG_IPADDR 192.162.1.2 73 # define CONFIG_NETMASK 255.255.255.0 74 # define CONFIG_SERVERIP 192.162.1.1 75 # define CONFIG_GATEWAYIP 192.162.1.1 76 #endif /* CONFIG_MCFFEC */ 77 78 #define CONFIG_HOSTNAME M5282EVB 79 #define CONFIG_EXTRA_ENV_SETTINGS \ 80 "netdev=eth0\0" \ 81 "loadaddr=10000\0" \ 82 "u-boot=u-boot.bin\0" \ 83 "load=tftp ${loadaddr) ${u-boot}\0" \ 84 "upd=run load; run prog\0" \ 85 "prog=prot off ffe00000 ffe3ffff;" \ 86 "era ffe00000 ffe3ffff;" \ 87 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 88 "save\0" \ 89 "" 90 91 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 92 93 #define CONFIG_SYS_LOAD_ADDR 0x20000 94 95 #define CONFIG_SYS_MEMTEST_START 0x400 96 #define CONFIG_SYS_MEMTEST_END 0x380000 97 98 #define CONFIG_SYS_CLK 64000000 99 100 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 101 102 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 103 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 104 105 /* 106 * Low Level Configuration Settings 107 * (address mappings, register initial values, etc.) 108 * You should know what you are doing if you make changes here. 109 */ 110 #define CONFIG_SYS_MBAR 0x40000000 111 112 /*----------------------------------------------------------------------- 113 * Definitions for initial stack pointer and data area (in DPRAM) 114 */ 115 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 116 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 117 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 118 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 119 120 /*----------------------------------------------------------------------- 121 * Start addresses for the final memory configuration 122 * (Set up by the startup code) 123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 124 */ 125 #define CONFIG_SYS_SDRAM_BASE 0x00000000 126 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 127 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 128 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 129 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 130 131 /* If M5282 port is fully implemented the monitor base will be behind 132 * the vector table. */ 133 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 134 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 135 #else 136 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 137 #endif 138 139 #define CONFIG_SYS_MONITOR_LEN 0x20000 140 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 141 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 142 143 /* 144 * For booting Linux, the board info and command line data 145 * have to be in the first 8 MB of memory, since this is 146 * the maximum mapped by the Linux kernel during initialization ?? 147 */ 148 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 149 150 /*----------------------------------------------------------------------- 151 * FLASH organization 152 */ 153 #define CONFIG_SYS_FLASH_CFI 154 #ifdef CONFIG_SYS_FLASH_CFI 155 156 # define CONFIG_FLASH_CFI_DRIVER 1 157 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 158 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 159 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 160 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 161 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 162 # define CONFIG_SYS_FLASH_CHECKSUM 163 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 164 #endif 165 166 /*----------------------------------------------------------------------- 167 * Cache Configuration 168 */ 169 #define CONFIG_SYS_CACHELINE_SIZE 16 170 171 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 172 CONFIG_SYS_INIT_RAM_SIZE - 8) 173 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 174 CONFIG_SYS_INIT_RAM_SIZE - 4) 175 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 176 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 177 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 178 CF_ACR_EN | CF_ACR_SM_ALL) 179 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 180 CF_CACR_CEIB | CF_CACR_DBWE | \ 181 CF_CACR_EUSP) 182 183 /*----------------------------------------------------------------------- 184 * Memory bank definitions 185 */ 186 #define CONFIG_SYS_CS0_BASE 0xFFE00000 187 #define CONFIG_SYS_CS0_CTRL 0x00001980 188 #define CONFIG_SYS_CS0_MASK 0x001F0001 189 190 /*----------------------------------------------------------------------- 191 * Port configuration 192 */ 193 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 194 #define CONFIG_SYS_PADDR 0x0000000 195 #define CONFIG_SYS_PADAT 0x0000000 196 197 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 198 #define CONFIG_SYS_PBDDR 0x0000000 199 #define CONFIG_SYS_PBDAT 0x0000000 200 201 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 202 #define CONFIG_SYS_PCDDR 0x0000000 203 #define CONFIG_SYS_PCDAT 0x0000000 204 205 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 206 #define CONFIG_SYS_PCDDR 0x0000000 207 #define CONFIG_SYS_PCDAT 0x0000000 208 209 #define CONFIG_SYS_PEHLPAR 0xC0 210 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 211 #define CONFIG_SYS_DDRUA 0x05 212 #define CONFIG_SYS_PJPAR 0xFF 213 214 #endif /* _CONFIG_M5282EVB_H */ 215