1 /* 2 * Configuation settings for the Motorola MC5282EVB board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _CONFIG_M5282EVB_H 14 #define _CONFIG_M5282EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 27 28 /* Configuration for environment 29 * Environment is embedded in u-boot in the second sector of the flash 30 */ 31 #define CONFIG_ENV_ADDR 0xffe04000 32 #define CONFIG_ENV_SIZE 0x2000 33 #define CONFIG_ENV_IS_IN_FLASH 1 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text*); 38 39 /* 40 * BOOTP options 41 */ 42 #define CONFIG_BOOTP_BOOTFILESIZE 43 #define CONFIG_BOOTP_BOOTPATH 44 #define CONFIG_BOOTP_GATEWAY 45 #define CONFIG_BOOTP_HOSTNAME 46 47 /* 48 * Command line configuration. 49 */ 50 #define CONFIG_CMD_CACHE 51 #define CONFIG_CMD_PING 52 #define CONFIG_CMD_MII 53 54 #define CONFIG_MCFFEC 55 #ifdef CONFIG_MCFFEC 56 # define CONFIG_MII 1 57 # define CONFIG_MII_INIT 1 58 # define CONFIG_SYS_DISCOVER_PHY 59 # define CONFIG_SYS_RX_ETH_BUFFER 8 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 62 # define CONFIG_SYS_FEC0_PINMUX 0 63 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 64 # define MCFFEC_TOUT_LOOP 50000 65 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 66 # ifndef CONFIG_SYS_DISCOVER_PHY 67 # define FECDUPLEX FULL 68 # define FECSPEED _100BASET 69 # else 70 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 72 # endif 73 # endif /* CONFIG_SYS_DISCOVER_PHY */ 74 #endif 75 76 #define CONFIG_BOOTDELAY 5 77 #ifdef CONFIG_MCFFEC 78 # define CONFIG_IPADDR 192.162.1.2 79 # define CONFIG_NETMASK 255.255.255.0 80 # define CONFIG_SERVERIP 192.162.1.1 81 # define CONFIG_GATEWAYIP 192.162.1.1 82 #endif /* CONFIG_MCFFEC */ 83 84 #define CONFIG_HOSTNAME M5282EVB 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 "netdev=eth0\0" \ 87 "loadaddr=10000\0" \ 88 "u-boot=u-boot.bin\0" \ 89 "load=tftp ${loadaddr) ${u-boot}\0" \ 90 "upd=run load; run prog\0" \ 91 "prog=prot off ffe00000 ffe3ffff;" \ 92 "era ffe00000 ffe3ffff;" \ 93 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 94 "save\0" \ 95 "" 96 97 #define CONFIG_SYS_PROMPT "-> " 98 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 99 100 #if defined(CONFIG_CMD_KGDB) 101 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 102 #else 103 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 104 #endif 105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 106 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 108 109 #define CONFIG_SYS_LOAD_ADDR 0x20000 110 111 #define CONFIG_SYS_MEMTEST_START 0x400 112 #define CONFIG_SYS_MEMTEST_END 0x380000 113 114 #define CONFIG_SYS_CLK 64000000 115 116 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 117 118 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 119 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 120 121 /* 122 * Low Level Configuration Settings 123 * (address mappings, register initial values, etc.) 124 * You should know what you are doing if you make changes here. 125 */ 126 #define CONFIG_SYS_MBAR 0x40000000 127 128 /*----------------------------------------------------------------------- 129 * Definitions for initial stack pointer and data area (in DPRAM) 130 */ 131 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 132 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 135 136 /*----------------------------------------------------------------------- 137 * Start addresses for the final memory configuration 138 * (Set up by the startup code) 139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 140 */ 141 #define CONFIG_SYS_SDRAM_BASE 0x00000000 142 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 143 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 144 #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 145 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 146 147 /* If M5282 port is fully implemented the monitor base will be behind 148 * the vector table. */ 149 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 150 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 151 #else 152 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 153 #endif 154 155 #define CONFIG_SYS_MONITOR_LEN 0x20000 156 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 157 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 158 159 /* 160 * For booting Linux, the board info and command line data 161 * have to be in the first 8 MB of memory, since this is 162 * the maximum mapped by the Linux kernel during initialization ?? 163 */ 164 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 165 166 /*----------------------------------------------------------------------- 167 * FLASH organization 168 */ 169 #define CONFIG_SYS_FLASH_CFI 170 #ifdef CONFIG_SYS_FLASH_CFI 171 172 # define CONFIG_FLASH_CFI_DRIVER 1 173 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 174 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 175 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 176 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 177 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 178 # define CONFIG_SYS_FLASH_CHECKSUM 179 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 180 #endif 181 182 /*----------------------------------------------------------------------- 183 * Cache Configuration 184 */ 185 #define CONFIG_SYS_CACHELINE_SIZE 16 186 187 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 188 CONFIG_SYS_INIT_RAM_SIZE - 8) 189 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 190 CONFIG_SYS_INIT_RAM_SIZE - 4) 191 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 192 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 193 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 194 CF_ACR_EN | CF_ACR_SM_ALL) 195 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 196 CF_CACR_CEIB | CF_CACR_DBWE | \ 197 CF_CACR_EUSP) 198 199 /*----------------------------------------------------------------------- 200 * Memory bank definitions 201 */ 202 #define CONFIG_SYS_CS0_BASE 0xFFE00000 203 #define CONFIG_SYS_CS0_CTRL 0x00001980 204 #define CONFIG_SYS_CS0_MASK 0x001F0001 205 206 /*----------------------------------------------------------------------- 207 * Port configuration 208 */ 209 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 210 #define CONFIG_SYS_PADDR 0x0000000 211 #define CONFIG_SYS_PADAT 0x0000000 212 213 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 214 #define CONFIG_SYS_PBDDR 0x0000000 215 #define CONFIG_SYS_PBDAT 0x0000000 216 217 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 218 #define CONFIG_SYS_PCDDR 0x0000000 219 #define CONFIG_SYS_PCDAT 0x0000000 220 221 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 222 #define CONFIG_SYS_PCDDR 0x0000000 223 #define CONFIG_SYS_PCDAT 0x0000000 224 225 #define CONFIG_SYS_PEHLPAR 0xC0 226 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 227 #define CONFIG_SYS_DDRUA 0x05 228 #define CONFIG_SYS_PJPAR 0xFF 229 230 #endif /* _CONFIG_M5282EVB_H */ 231