1 /* 2 * Configuation settings for the Motorola MC5275EVB board. 3 * 4 * By Arthur Shipkowski <art@videon-central.com> 5 * Copyright (C) 2005 Videon Central, Inc. 6 * 7 * Based off of M5272C3 board code by Josef Baumgartner 8 * <josef.baumgartner@telex.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * board/config.h - configuration options, board specific 15 */ 16 17 #ifndef _M5275EVB_H 18 #define _M5275EVB_H 19 20 /* 21 * High Level Configuration Options 22 * (easy to change) 23 */ 24 25 #define CONFIG_MCFTMR 26 27 #define CONFIG_MCFUART 28 #define CONFIG_SYS_UART_PORT (0) 29 30 /* Configuration for environment 31 * Environment is embedded in u-boot in the second sector of the flash 32 */ 33 #ifndef CONFIG_MONITOR_IS_IN_RAM 34 #define CONFIG_ENV_OFFSET 0x4000 35 #define CONFIG_ENV_SECT_SIZE 0x2000 36 #else 37 #define CONFIG_ENV_ADDR 0xffe04000 38 #define CONFIG_ENV_SECT_SIZE 0x2000 39 #endif 40 41 #define LDS_BOARD_TEXT \ 42 . = DEFINED(env_offset) ? env_offset : .; \ 43 env/embedded.o(.text); 44 45 /* 46 * BOOTP options 47 */ 48 #define CONFIG_BOOTP_BOOTFILESIZE 49 50 /* Available command configuration */ 51 52 #define CONFIG_MCFFEC 53 #ifdef CONFIG_MCFFEC 54 #define CONFIG_MII 1 55 #define CONFIG_MII_INIT 1 56 #define CONFIG_SYS_DISCOVER_PHY 57 #define CONFIG_SYS_RX_ETH_BUFFER 8 58 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 #define CONFIG_SYS_FEC0_PINMUX 0 60 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 61 #define CONFIG_SYS_FEC1_PINMUX 0 62 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 63 #define MCFFEC_TOUT_LOOP 50000 64 #define CONFIG_HAS_ETH1 65 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 66 #ifndef CONFIG_SYS_DISCOVER_PHY 67 #define FECDUPLEX FULL 68 #define FECSPEED _100BASET 69 #else 70 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 72 #endif 73 #endif 74 #endif 75 76 /* I2C */ 77 #define CONFIG_SYS_I2C 78 #define CONFIG_SYS_I2C_FSL 79 #define CONFIG_SYS_FSL_I2C_SPEED 80000 80 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 81 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 82 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 83 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 84 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 85 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 86 87 #define CONFIG_SYS_LOAD_ADDR 0x800000 88 89 #define CONFIG_BOOTCOMMAND "bootm ffe40000" 90 #define CONFIG_SYS_MEMTEST_START 0x400 91 #define CONFIG_SYS_MEMTEST_END 0x380000 92 93 #ifdef CONFIG_MCFFEC 94 # define CONFIG_NET_RETRY_COUNT 5 95 # define CONFIG_OVERWRITE_ETHADDR_ONCE 96 #endif /* FEC_ENET */ 97 98 #define CONFIG_EXTRA_ENV_SETTINGS \ 99 "netdev=eth0\0" \ 100 "loadaddr=10000\0" \ 101 "uboot=u-boot.bin\0" \ 102 "load=tftp ${loadaddr} ${uboot}\0" \ 103 "upd=run load; run prog\0" \ 104 "prog=prot off ffe00000 ffe3ffff;" \ 105 "era ffe00000 ffe3ffff;" \ 106 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 107 "save\0" \ 108 "" 109 110 #define CONFIG_SYS_CLK 150000000 111 112 /* 113 * Low Level Configuration Settings 114 * (address mappings, register initial values, etc.) 115 * You should know what you are doing if you make changes here. 116 */ 117 118 #define CONFIG_SYS_MBAR 0x40000000 119 120 /*----------------------------------------------------------------------- 121 * Definitions for initial stack pointer and data area (in DPRAM) 122 */ 123 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 124 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 125 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 126 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 127 128 /*----------------------------------------------------------------------- 129 * Start addresses for the final memory configuration 130 * (Set up by the startup code) 131 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 132 */ 133 #define CONFIG_SYS_SDRAM_BASE 0x00000000 134 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 135 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 136 137 #ifdef CONFIG_MONITOR_IS_IN_RAM 138 #define CONFIG_SYS_MONITOR_BASE 0x20000 139 #else 140 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 141 #endif 142 143 #define CONFIG_SYS_MONITOR_LEN 0x20000 144 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 145 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 146 147 /* 148 * For booting Linux, the board info and command line data 149 * have to be in the first 8 MB of memory, since this is 150 * the maximum mapped by the Linux kernel during initialization ?? 151 */ 152 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 153 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 154 155 /*----------------------------------------------------------------------- 156 * FLASH organization 157 */ 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 159 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 160 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 161 162 #define CONFIG_SYS_FLASH_CFI 1 163 #define CONFIG_FLASH_CFI_DRIVER 1 164 #define CONFIG_SYS_FLASH_SIZE 0x200000 165 166 /*----------------------------------------------------------------------- 167 * Cache Configuration 168 */ 169 #define CONFIG_SYS_CACHELINE_SIZE 16 170 171 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 172 CONFIG_SYS_INIT_RAM_SIZE - 8) 173 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 174 CONFIG_SYS_INIT_RAM_SIZE - 4) 175 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 176 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 177 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 178 CF_ACR_EN | CF_ACR_SM_ALL) 179 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 180 CF_CACR_DISD | CF_CACR_INVI | \ 181 CF_CACR_CEIB | CF_CACR_DCM | \ 182 CF_CACR_EUSP) 183 184 /*----------------------------------------------------------------------- 185 * Memory bank definitions 186 */ 187 #define CONFIG_SYS_CS0_BASE 0xffe00000 188 #define CONFIG_SYS_CS0_CTRL 0x00001980 189 #define CONFIG_SYS_CS0_MASK 0x001F0001 190 191 #define CONFIG_SYS_CS1_BASE 0x30000000 192 #define CONFIG_SYS_CS1_CTRL 0x00001900 193 #define CONFIG_SYS_CS1_MASK 0x00070001 194 195 /*----------------------------------------------------------------------- 196 * Port configuration 197 */ 198 #define CONFIG_SYS_FECI2C 0x0FA0 199 200 #endif /* _M5275EVB_H */ 201