1 /* 2 * Configuation settings for the Motorola MC5275EVB board. 3 * 4 * By Arthur Shipkowski <art@videon-central.com> 5 * Copyright (C) 2005 Videon Central, Inc. 6 * 7 * Based off of M5272C3 board code by Josef Baumgartner 8 * <josef.baumgartner@telex.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * board/config.h - configuration options, board specific 15 */ 16 17 #ifndef _M5275EVB_H 18 #define _M5275EVB_H 19 20 /* 21 * High Level Configuration Options 22 * (easy to change) 23 */ 24 #define CONFIG_MCF52x2 /* define processor family */ 25 #define CONFIG_M5275 /* define processor type */ 26 #define CONFIG_M5275EVB /* define board type */ 27 28 #define CONFIG_MCFTMR 29 30 #define CONFIG_MCFUART 31 #define CONFIG_SYS_UART_PORT (0) 32 #define CONFIG_BAUDRATE 115200 33 34 /* Configuration for environment 35 * Environment is embedded in u-boot in the second sector of the flash 36 */ 37 #ifndef CONFIG_MONITOR_IS_IN_RAM 38 #define CONFIG_ENV_OFFSET 0x4000 39 #define CONFIG_ENV_SECT_SIZE 0x2000 40 #define CONFIG_ENV_IS_IN_FLASH 1 41 #else 42 #define CONFIG_ENV_ADDR 0xffe04000 43 #define CONFIG_ENV_SECT_SIZE 0x2000 44 #define CONFIG_ENV_IS_IN_FLASH 1 45 #endif 46 47 /* 48 * BOOTP options 49 */ 50 #define CONFIG_BOOTP_BOOTFILESIZE 51 #define CONFIG_BOOTP_BOOTPATH 52 #define CONFIG_BOOTP_GATEWAY 53 #define CONFIG_BOOTP_HOSTNAME 54 55 /* Available command configuration */ 56 #include <config_cmd_default.h> 57 58 #define CONFIG_CMD_CACHE 59 #define CONFIG_CMD_PING 60 #define CONFIG_CMD_MII 61 #define CONFIG_CMD_NET 62 #define CONFIG_CMD_ELF 63 #define CONFIG_CMD_FLASH 64 #define CONFIG_CMD_I2C 65 #define CONFIG_CMD_MEMORY 66 #define CONFIG_CMD_DHCP 67 68 #undef CONFIG_CMD_LOADS 69 #undef CONFIG_CMD_LOADB 70 71 #define CONFIG_MCFFEC 72 #ifdef CONFIG_MCFFEC 73 #define CONFIG_MII 1 74 #define CONFIG_MII_INIT 1 75 #define CONFIG_SYS_DISCOVER_PHY 76 #define CONFIG_SYS_RX_ETH_BUFFER 8 77 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 78 #define CONFIG_SYS_FEC0_PINMUX 0 79 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 80 #define CONFIG_SYS_FEC1_PINMUX 0 81 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 82 #define MCFFEC_TOUT_LOOP 50000 83 #define CONFIG_HAS_ETH1 84 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 85 #ifndef CONFIG_SYS_DISCOVER_PHY 86 #define FECDUPLEX FULL 87 #define FECSPEED _100BASET 88 #else 89 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 90 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 91 #endif 92 #endif 93 #endif 94 95 /* I2C */ 96 #define CONFIG_SYS_I2C 97 #define CONFIG_SYS_I2C_FSL 98 #define CONFIG_SYS_FSL_I2C_SPEED 80000 99 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 100 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 101 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 102 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 103 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 104 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 105 106 #define CONFIG_SYS_PROMPT "-> " 107 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 108 109 #if (CONFIG_CMD_KGDB) 110 # define CONFIG_SYS_CBSIZE 1024 111 #else 112 # define CONFIG_SYS_CBSIZE 256 113 #endif 114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 115 #define CONFIG_SYS_MAXARGS 16 116 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 117 118 #define CONFIG_SYS_LOAD_ADDR 0x800000 119 120 #define CONFIG_BOOTDELAY 5 121 #define CONFIG_BOOTCOMMAND "bootm ffe40000" 122 #define CONFIG_SYS_MEMTEST_START 0x400 123 #define CONFIG_SYS_MEMTEST_END 0x380000 124 125 #ifdef CONFIG_MCFFEC 126 # define CONFIG_NET_RETRY_COUNT 5 127 # define CONFIG_OVERWRITE_ETHADDR_ONCE 128 #endif /* FEC_ENET */ 129 130 #define CONFIG_EXTRA_ENV_SETTINGS \ 131 "netdev=eth0\0" \ 132 "loadaddr=10000\0" \ 133 "uboot=u-boot.bin\0" \ 134 "load=tftp ${loadaddr} ${uboot}\0" \ 135 "upd=run load; run prog\0" \ 136 "prog=prot off ffe00000 ffe3ffff;" \ 137 "era ffe00000 ffe3ffff;" \ 138 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 139 "save\0" \ 140 "" 141 142 #define CONFIG_SYS_HZ 1000 143 #define CONFIG_SYS_CLK 150000000 144 145 /* 146 * Low Level Configuration Settings 147 * (address mappings, register initial values, etc.) 148 * You should know what you are doing if you make changes here. 149 */ 150 151 #define CONFIG_SYS_MBAR 0x40000000 152 153 /*----------------------------------------------------------------------- 154 * Definitions for initial stack pointer and data area (in DPRAM) 155 */ 156 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 157 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 158 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 161 /*----------------------------------------------------------------------- 162 * Start addresses for the final memory configuration 163 * (Set up by the startup code) 164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 165 */ 166 #define CONFIG_SYS_SDRAM_BASE 0x00000000 167 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 168 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 169 170 #ifdef CONFIG_MONITOR_IS_IN_RAM 171 #define CONFIG_SYS_MONITOR_BASE 0x20000 172 #else 173 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 174 #endif 175 176 #define CONFIG_SYS_MONITOR_LEN 0x20000 177 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 178 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 179 180 /* 181 * For booting Linux, the board info and command line data 182 * have to be in the first 8 MB of memory, since this is 183 * the maximum mapped by the Linux kernel during initialization ?? 184 */ 185 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 186 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 187 188 /*----------------------------------------------------------------------- 189 * FLASH organization 190 */ 191 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 192 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 193 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 194 195 #define CONFIG_SYS_FLASH_CFI 1 196 #define CONFIG_FLASH_CFI_DRIVER 1 197 #define CONFIG_SYS_FLASH_SIZE 0x200000 198 199 /*----------------------------------------------------------------------- 200 * Cache Configuration 201 */ 202 #define CONFIG_SYS_CACHELINE_SIZE 16 203 204 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 205 CONFIG_SYS_INIT_RAM_SIZE - 8) 206 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 4) 208 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 209 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 210 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 211 CF_ACR_EN | CF_ACR_SM_ALL) 212 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 213 CF_CACR_DISD | CF_CACR_INVI | \ 214 CF_CACR_CEIB | CF_CACR_DCM | \ 215 CF_CACR_EUSP) 216 217 /*----------------------------------------------------------------------- 218 * Memory bank definitions 219 */ 220 #define CONFIG_SYS_CS0_BASE 0xffe00000 221 #define CONFIG_SYS_CS0_CTRL 0x00001980 222 #define CONFIG_SYS_CS0_MASK 0x001F0001 223 224 #define CONFIG_SYS_CS1_BASE 0x30000000 225 #define CONFIG_SYS_CS1_CTRL 0x00001900 226 #define CONFIG_SYS_CS1_MASK 0x00070001 227 228 /*----------------------------------------------------------------------- 229 * Port configuration 230 */ 231 #define CONFIG_SYS_FECI2C 0x0FA0 232 233 #endif /* _M5275EVB_H */ 234