1 /* 2 * Configuation settings for the Motorola MC5275EVB board. 3 * 4 * By Arthur Shipkowski <art@videon-central.com> 5 * Copyright (C) 2005 Videon Central, Inc. 6 * 7 * Based off of M5272C3 board code by Josef Baumgartner 8 * <josef.baumgartner@telex.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * board/config.h - configuration options, board specific 15 */ 16 17 #ifndef _M5275EVB_H 18 #define _M5275EVB_H 19 20 /* 21 * High Level Configuration Options 22 * (easy to change) 23 */ 24 #define CONFIG_M5275EVB /* define board type */ 25 26 #define CONFIG_MCFTMR 27 28 #define CONFIG_MCFUART 29 #define CONFIG_SYS_UART_PORT (0) 30 #define CONFIG_BAUDRATE 115200 31 32 /* Configuration for environment 33 * Environment is embedded in u-boot in the second sector of the flash 34 */ 35 #ifndef CONFIG_MONITOR_IS_IN_RAM 36 #define CONFIG_ENV_OFFSET 0x4000 37 #define CONFIG_ENV_SECT_SIZE 0x2000 38 #define CONFIG_ENV_IS_IN_FLASH 1 39 #else 40 #define CONFIG_ENV_ADDR 0xffe04000 41 #define CONFIG_ENV_SECT_SIZE 0x2000 42 #define CONFIG_ENV_IS_IN_FLASH 1 43 #endif 44 45 #define LDS_BOARD_TEXT \ 46 . = DEFINED(env_offset) ? env_offset : .; \ 47 common/env_embedded.o (.text); 48 49 /* 50 * BOOTP options 51 */ 52 #define CONFIG_BOOTP_BOOTFILESIZE 53 #define CONFIG_BOOTP_BOOTPATH 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_BOOTP_HOSTNAME 56 57 /* Available command configuration */ 58 #define CONFIG_CMD_CACHE 59 #define CONFIG_CMD_PING 60 #define CONFIG_CMD_MII 61 #define CONFIG_CMD_ELF 62 #define CONFIG_CMD_I2C 63 #define CONFIG_CMD_DHCP 64 65 66 #define CONFIG_MCFFEC 67 #ifdef CONFIG_MCFFEC 68 #define CONFIG_MII 1 69 #define CONFIG_MII_INIT 1 70 #define CONFIG_SYS_DISCOVER_PHY 71 #define CONFIG_SYS_RX_ETH_BUFFER 8 72 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 73 #define CONFIG_SYS_FEC0_PINMUX 0 74 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 75 #define CONFIG_SYS_FEC1_PINMUX 0 76 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE 77 #define MCFFEC_TOUT_LOOP 50000 78 #define CONFIG_HAS_ETH1 79 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 80 #ifndef CONFIG_SYS_DISCOVER_PHY 81 #define FECDUPLEX FULL 82 #define FECSPEED _100BASET 83 #else 84 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 85 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 86 #endif 87 #endif 88 #endif 89 90 /* I2C */ 91 #define CONFIG_SYS_I2C 92 #define CONFIG_SYS_I2C_FSL 93 #define CONFIG_SYS_FSL_I2C_SPEED 80000 94 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 95 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 96 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 97 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 98 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 99 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 100 101 #define CONFIG_SYS_PROMPT "-> " 102 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 103 104 #if (CONFIG_CMD_KGDB) 105 # define CONFIG_SYS_CBSIZE 1024 106 #else 107 # define CONFIG_SYS_CBSIZE 256 108 #endif 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 110 #define CONFIG_SYS_MAXARGS 16 111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 112 113 #define CONFIG_SYS_LOAD_ADDR 0x800000 114 115 #define CONFIG_BOOTDELAY 5 116 #define CONFIG_BOOTCOMMAND "bootm ffe40000" 117 #define CONFIG_SYS_MEMTEST_START 0x400 118 #define CONFIG_SYS_MEMTEST_END 0x380000 119 120 #ifdef CONFIG_MCFFEC 121 # define CONFIG_NET_RETRY_COUNT 5 122 # define CONFIG_OVERWRITE_ETHADDR_ONCE 123 #endif /* FEC_ENET */ 124 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "netdev=eth0\0" \ 127 "loadaddr=10000\0" \ 128 "uboot=u-boot.bin\0" \ 129 "load=tftp ${loadaddr} ${uboot}\0" \ 130 "upd=run load; run prog\0" \ 131 "prog=prot off ffe00000 ffe3ffff;" \ 132 "era ffe00000 ffe3ffff;" \ 133 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 134 "save\0" \ 135 "" 136 137 #define CONFIG_SYS_CLK 150000000 138 139 /* 140 * Low Level Configuration Settings 141 * (address mappings, register initial values, etc.) 142 * You should know what you are doing if you make changes here. 143 */ 144 145 #define CONFIG_SYS_MBAR 0x40000000 146 147 /*----------------------------------------------------------------------- 148 * Definitions for initial stack pointer and data area (in DPRAM) 149 */ 150 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 152 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 155 /*----------------------------------------------------------------------- 156 * Start addresses for the final memory configuration 157 * (Set up by the startup code) 158 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 159 */ 160 #define CONFIG_SYS_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 162 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 163 164 #ifdef CONFIG_MONITOR_IS_IN_RAM 165 #define CONFIG_SYS_MONITOR_BASE 0x20000 166 #else 167 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 168 #endif 169 170 #define CONFIG_SYS_MONITOR_LEN 0x20000 171 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 172 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 173 174 /* 175 * For booting Linux, the board info and command line data 176 * have to be in the first 8 MB of memory, since this is 177 * the maximum mapped by the Linux kernel during initialization ?? 178 */ 179 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 180 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 181 182 /*----------------------------------------------------------------------- 183 * FLASH organization 184 */ 185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 187 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 188 189 #define CONFIG_SYS_FLASH_CFI 1 190 #define CONFIG_FLASH_CFI_DRIVER 1 191 #define CONFIG_SYS_FLASH_SIZE 0x200000 192 193 /*----------------------------------------------------------------------- 194 * Cache Configuration 195 */ 196 #define CONFIG_SYS_CACHELINE_SIZE 16 197 198 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 199 CONFIG_SYS_INIT_RAM_SIZE - 8) 200 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 201 CONFIG_SYS_INIT_RAM_SIZE - 4) 202 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 203 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 204 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 205 CF_ACR_EN | CF_ACR_SM_ALL) 206 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 207 CF_CACR_DISD | CF_CACR_INVI | \ 208 CF_CACR_CEIB | CF_CACR_DCM | \ 209 CF_CACR_EUSP) 210 211 /*----------------------------------------------------------------------- 212 * Memory bank definitions 213 */ 214 #define CONFIG_SYS_CS0_BASE 0xffe00000 215 #define CONFIG_SYS_CS0_CTRL 0x00001980 216 #define CONFIG_SYS_CS0_MASK 0x001F0001 217 218 #define CONFIG_SYS_CS1_BASE 0x30000000 219 #define CONFIG_SYS_CS1_CTRL 0x00001900 220 #define CONFIG_SYS_CS1_MASK 0x00070001 221 222 /*----------------------------------------------------------------------- 223 * Port configuration 224 */ 225 #define CONFIG_SYS_FECI2C 0x0FA0 226 227 #endif /* _M5275EVB_H */ 228