1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Motorola MC5272C3 board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8 /* 9 * board/config.h - configuration options, board specific 10 */ 11 12 #ifndef _M5272C3_H 13 #define _M5272C3_H 14 15 /* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 #define CONFIG_MCFTMR 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 26 27 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 28 29 /* Configuration for environment 30 * Environment is embedded in u-boot in the second sector of the flash 31 */ 32 #ifndef CONFIG_MONITOR_IS_IN_RAM 33 #define CONFIG_ENV_OFFSET 0x4000 34 #define CONFIG_ENV_SECT_SIZE 0x2000 35 #else 36 #define CONFIG_ENV_ADDR 0xffe04000 37 #define CONFIG_ENV_SECT_SIZE 0x2000 38 #endif 39 40 #define LDS_BOARD_TEXT \ 41 . = DEFINED(env_offset) ? env_offset : .; \ 42 env/embedded.o(.text); 43 44 /* 45 * BOOTP options 46 */ 47 #define CONFIG_BOOTP_BOOTFILESIZE 48 49 /* 50 * Command line configuration. 51 */ 52 53 #define CONFIG_MCFFEC 54 #ifdef CONFIG_MCFFEC 55 # define CONFIG_MII_INIT 1 56 # define CONFIG_SYS_DISCOVER_PHY 57 # define CONFIG_SYS_RX_ETH_BUFFER 8 58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 60 # define CONFIG_SYS_FEC0_PINMUX 0 61 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 62 # define MCFFEC_TOUT_LOOP 50000 63 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 64 # ifndef CONFIG_SYS_DISCOVER_PHY 65 # define FECDUPLEX FULL 66 # define FECSPEED _100BASET 67 # else 68 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 69 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # endif 71 # endif /* CONFIG_SYS_DISCOVER_PHY */ 72 #endif 73 74 #ifdef CONFIG_MCFFEC 75 # define CONFIG_IPADDR 192.162.1.2 76 # define CONFIG_NETMASK 255.255.255.0 77 # define CONFIG_SERVERIP 192.162.1.1 78 # define CONFIG_GATEWAYIP 192.162.1.1 79 #endif /* CONFIG_MCFFEC */ 80 81 #define CONFIG_HOSTNAME "M5272C3" 82 #define CONFIG_EXTRA_ENV_SETTINGS \ 83 "netdev=eth0\0" \ 84 "loadaddr=10000\0" \ 85 "u-boot=u-boot.bin\0" \ 86 "load=tftp ${loadaddr) ${u-boot}\0" \ 87 "upd=run load; run prog\0" \ 88 "prog=prot off ffe00000 ffe3ffff;" \ 89 "era ffe00000 ffe3ffff;" \ 90 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 91 "save\0" \ 92 "" 93 94 #define CONFIG_SYS_LOAD_ADDR 0x20000 95 #define CONFIG_SYS_MEMTEST_START 0x400 96 #define CONFIG_SYS_MEMTEST_END 0x380000 97 #define CONFIG_SYS_CLK 66000000 98 99 /* 100 * Low Level Configuration Settings 101 * (address mappings, register initial values, etc.) 102 * You should know what you are doing if you make changes here. 103 */ 104 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 105 #define CONFIG_SYS_SCR 0x0003 106 #define CONFIG_SYS_SPR 0xffff 107 108 /*----------------------------------------------------------------------- 109 * Definitions for initial stack pointer and data area (in DPRAM) 110 */ 111 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 112 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 113 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 114 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 115 116 /*----------------------------------------------------------------------- 117 * Start addresses for the final memory configuration 118 * (Set up by the startup code) 119 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 120 */ 121 #define CONFIG_SYS_SDRAM_BASE 0x00000000 122 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 123 #define CONFIG_SYS_FLASH_BASE 0xffe00000 124 125 #ifdef CONFIG_MONITOR_IS_IN_RAM 126 #define CONFIG_SYS_MONITOR_BASE 0x20000 127 #else 128 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 129 #endif 130 131 #define CONFIG_SYS_MONITOR_LEN 0x20000 132 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 133 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 134 135 /* 136 * For booting Linux, the board info and command line data 137 * have to be in the first 8 MB of memory, since this is 138 * the maximum mapped by the Linux kernel during initialization ?? 139 */ 140 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 141 142 /* 143 * FLASH organization 144 */ 145 #define CONFIG_SYS_FLASH_CFI 146 #ifdef CONFIG_SYS_FLASH_CFI 147 # define CONFIG_FLASH_CFI_DRIVER 1 148 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 149 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 150 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 151 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 152 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 153 #endif 154 155 /*----------------------------------------------------------------------- 156 * Cache Configuration 157 */ 158 #define CONFIG_SYS_CACHELINE_SIZE 16 159 160 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 161 CONFIG_SYS_INIT_RAM_SIZE - 8) 162 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 163 CONFIG_SYS_INIT_RAM_SIZE - 4) 164 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 165 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 166 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 167 CF_ACR_EN | CF_ACR_SM_ALL) 168 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 169 CF_CACR_DISD | CF_CACR_INVI | \ 170 CF_CACR_CEIB | CF_CACR_DCM | \ 171 CF_CACR_EUSP) 172 173 /*----------------------------------------------------------------------- 174 * Memory bank definitions 175 */ 176 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 177 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 178 #define CONFIG_SYS_BR1_PRELIM 0 179 #define CONFIG_SYS_OR1_PRELIM 0 180 #define CONFIG_SYS_BR2_PRELIM 0x30000001 181 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 182 #define CONFIG_SYS_BR3_PRELIM 0 183 #define CONFIG_SYS_OR3_PRELIM 0 184 #define CONFIG_SYS_BR4_PRELIM 0 185 #define CONFIG_SYS_OR4_PRELIM 0 186 #define CONFIG_SYS_BR5_PRELIM 0 187 #define CONFIG_SYS_OR5_PRELIM 0 188 #define CONFIG_SYS_BR6_PRELIM 0 189 #define CONFIG_SYS_OR6_PRELIM 0 190 #define CONFIG_SYS_BR7_PRELIM 0x00000701 191 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C 192 193 /*----------------------------------------------------------------------- 194 * Port configuration 195 */ 196 #define CONFIG_SYS_PACNT 0x00000000 197 #define CONFIG_SYS_PADDR 0x0000 198 #define CONFIG_SYS_PADAT 0x0000 199 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 200 #define CONFIG_SYS_PBDDR 0x0000 201 #define CONFIG_SYS_PBDAT 0x0000 202 #define CONFIG_SYS_PDCNT 0x00000000 203 #endif /* _M5272C3_H */ 204