1 /* 2 * Configuation settings for the Motorola MC5272C3 board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5272C3_H 14 #define _M5272C3_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 28 29 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 30 31 /* Configuration for environment 32 * Environment is embedded in u-boot in the second sector of the flash 33 */ 34 #ifndef CONFIG_MONITOR_IS_IN_RAM 35 #define CONFIG_ENV_OFFSET 0x4000 36 #define CONFIG_ENV_SECT_SIZE 0x2000 37 #define CONFIG_ENV_IS_IN_FLASH 1 38 #else 39 #define CONFIG_ENV_ADDR 0xffe04000 40 #define CONFIG_ENV_SECT_SIZE 0x2000 41 #define CONFIG_ENV_IS_IN_FLASH 1 42 #endif 43 44 #define LDS_BOARD_TEXT \ 45 . = DEFINED(env_offset) ? env_offset : .; \ 46 common/env_embedded.o (.text); 47 48 /* 49 * BOOTP options 50 */ 51 #define CONFIG_BOOTP_BOOTFILESIZE 52 #define CONFIG_BOOTP_BOOTPATH 53 #define CONFIG_BOOTP_GATEWAY 54 #define CONFIG_BOOTP_HOSTNAME 55 56 /* 57 * Command line configuration. 58 */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_CACHE 62 #define CONFIG_CMD_MII 63 #define CONFIG_CMD_PING 64 #define CONFIG_CMD_MISC 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_FLASH 67 #define CONFIG_CMD_MEMORY 68 69 #undef CONFIG_CMD_LOADS 70 #undef CONFIG_CMD_LOADB 71 72 #define CONFIG_BOOTDELAY 5 73 #define CONFIG_MCFFEC 74 #ifdef CONFIG_MCFFEC 75 # define CONFIG_MII 1 76 # define CONFIG_MII_INIT 1 77 # define CONFIG_SYS_DISCOVER_PHY 78 # define CONFIG_SYS_RX_ETH_BUFFER 8 79 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 80 81 # define CONFIG_SYS_FEC0_PINMUX 0 82 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 83 # define MCFFEC_TOUT_LOOP 50000 84 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 85 # ifndef CONFIG_SYS_DISCOVER_PHY 86 # define FECDUPLEX FULL 87 # define FECSPEED _100BASET 88 # else 89 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 90 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 91 # endif 92 # endif /* CONFIG_SYS_DISCOVER_PHY */ 93 #endif 94 95 #ifdef CONFIG_MCFFEC 96 # define CONFIG_IPADDR 192.162.1.2 97 # define CONFIG_NETMASK 255.255.255.0 98 # define CONFIG_SERVERIP 192.162.1.1 99 # define CONFIG_GATEWAYIP 192.162.1.1 100 #endif /* CONFIG_MCFFEC */ 101 102 #define CONFIG_HOSTNAME M5272C3 103 #define CONFIG_EXTRA_ENV_SETTINGS \ 104 "netdev=eth0\0" \ 105 "loadaddr=10000\0" \ 106 "u-boot=u-boot.bin\0" \ 107 "load=tftp ${loadaddr) ${u-boot}\0" \ 108 "upd=run load; run prog\0" \ 109 "prog=prot off ffe00000 ffe3ffff;" \ 110 "era ffe00000 ffe3ffff;" \ 111 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 112 "save\0" \ 113 "" 114 115 #define CONFIG_SYS_PROMPT "-> " 116 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 117 118 #if defined(CONFIG_CMD_KGDB) 119 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 120 #else 121 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 122 #endif 123 124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 125 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 127 #define CONFIG_SYS_LOAD_ADDR 0x20000 128 #define CONFIG_SYS_MEMTEST_START 0x400 129 #define CONFIG_SYS_MEMTEST_END 0x380000 130 #define CONFIG_SYS_CLK 66000000 131 132 /* 133 * Low Level Configuration Settings 134 * (address mappings, register initial values, etc.) 135 * You should know what you are doing if you make changes here. 136 */ 137 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 138 #define CONFIG_SYS_SCR 0x0003 139 #define CONFIG_SYS_SPR 0xffff 140 141 /*----------------------------------------------------------------------- 142 * Definitions for initial stack pointer and data area (in DPRAM) 143 */ 144 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 145 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 146 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 147 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 148 149 /*----------------------------------------------------------------------- 150 * Start addresses for the final memory configuration 151 * (Set up by the startup code) 152 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 153 */ 154 #define CONFIG_SYS_SDRAM_BASE 0x00000000 155 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 156 #define CONFIG_SYS_FLASH_BASE 0xffe00000 157 158 #ifdef CONFIG_MONITOR_IS_IN_RAM 159 #define CONFIG_SYS_MONITOR_BASE 0x20000 160 #else 161 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 162 #endif 163 164 #define CONFIG_SYS_MONITOR_LEN 0x20000 165 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 166 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 167 168 /* 169 * For booting Linux, the board info and command line data 170 * have to be in the first 8 MB of memory, since this is 171 * the maximum mapped by the Linux kernel during initialization ?? 172 */ 173 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 174 175 /* 176 * FLASH organization 177 */ 178 #define CONFIG_SYS_FLASH_CFI 179 #ifdef CONFIG_SYS_FLASH_CFI 180 # define CONFIG_FLASH_CFI_DRIVER 1 181 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 182 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 183 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 185 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 186 #endif 187 188 /*----------------------------------------------------------------------- 189 * Cache Configuration 190 */ 191 #define CONFIG_SYS_CACHELINE_SIZE 16 192 193 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 194 CONFIG_SYS_INIT_RAM_SIZE - 8) 195 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 196 CONFIG_SYS_INIT_RAM_SIZE - 4) 197 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 198 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 199 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 200 CF_ACR_EN | CF_ACR_SM_ALL) 201 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 202 CF_CACR_DISD | CF_CACR_INVI | \ 203 CF_CACR_CEIB | CF_CACR_DCM | \ 204 CF_CACR_EUSP) 205 206 /*----------------------------------------------------------------------- 207 * Memory bank definitions 208 */ 209 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 210 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 211 #define CONFIG_SYS_BR1_PRELIM 0 212 #define CONFIG_SYS_OR1_PRELIM 0 213 #define CONFIG_SYS_BR2_PRELIM 0x30000001 214 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 215 #define CONFIG_SYS_BR3_PRELIM 0 216 #define CONFIG_SYS_OR3_PRELIM 0 217 #define CONFIG_SYS_BR4_PRELIM 0 218 #define CONFIG_SYS_OR4_PRELIM 0 219 #define CONFIG_SYS_BR5_PRELIM 0 220 #define CONFIG_SYS_OR5_PRELIM 0 221 #define CONFIG_SYS_BR6_PRELIM 0 222 #define CONFIG_SYS_OR6_PRELIM 0 223 #define CONFIG_SYS_BR7_PRELIM 0x00000701 224 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C 225 226 /*----------------------------------------------------------------------- 227 * Port configuration 228 */ 229 #define CONFIG_SYS_PACNT 0x00000000 230 #define CONFIG_SYS_PADDR 0x0000 231 #define CONFIG_SYS_PADAT 0x0000 232 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 233 #define CONFIG_SYS_PBDDR 0x0000 234 #define CONFIG_SYS_PBDAT 0x0000 235 #define CONFIG_SYS_PDCNT 0x00000000 236 #endif /* _M5272C3_H */ 237