1 /* 2 * Configuation settings for the Motorola MC5272C3 board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5272C3_H 14 #define _M5272C3_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_MCFTMR 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 27 28 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 29 30 /* Configuration for environment 31 * Environment is embedded in u-boot in the second sector of the flash 32 */ 33 #ifndef CONFIG_MONITOR_IS_IN_RAM 34 #define CONFIG_ENV_OFFSET 0x4000 35 #define CONFIG_ENV_SECT_SIZE 0x2000 36 #define CONFIG_ENV_IS_IN_FLASH 1 37 #else 38 #define CONFIG_ENV_ADDR 0xffe04000 39 #define CONFIG_ENV_SECT_SIZE 0x2000 40 #define CONFIG_ENV_IS_IN_FLASH 1 41 #endif 42 43 #define LDS_BOARD_TEXT \ 44 . = DEFINED(env_offset) ? env_offset : .; \ 45 common/env_embedded.o (.text); 46 47 /* 48 * BOOTP options 49 */ 50 #define CONFIG_BOOTP_BOOTFILESIZE 51 #define CONFIG_BOOTP_BOOTPATH 52 #define CONFIG_BOOTP_GATEWAY 53 #define CONFIG_BOOTP_HOSTNAME 54 55 /* 56 * Command line configuration. 57 */ 58 59 #define CONFIG_MCFFEC 60 #ifdef CONFIG_MCFFEC 61 # define CONFIG_MII 1 62 # define CONFIG_MII_INIT 1 63 # define CONFIG_SYS_DISCOVER_PHY 64 # define CONFIG_SYS_RX_ETH_BUFFER 8 65 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 67 # define CONFIG_SYS_FEC0_PINMUX 0 68 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 69 # define MCFFEC_TOUT_LOOP 50000 70 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 71 # ifndef CONFIG_SYS_DISCOVER_PHY 72 # define FECDUPLEX FULL 73 # define FECSPEED _100BASET 74 # else 75 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 77 # endif 78 # endif /* CONFIG_SYS_DISCOVER_PHY */ 79 #endif 80 81 #ifdef CONFIG_MCFFEC 82 # define CONFIG_IPADDR 192.162.1.2 83 # define CONFIG_NETMASK 255.255.255.0 84 # define CONFIG_SERVERIP 192.162.1.1 85 # define CONFIG_GATEWAYIP 192.162.1.1 86 #endif /* CONFIG_MCFFEC */ 87 88 #define CONFIG_HOSTNAME M5272C3 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "netdev=eth0\0" \ 91 "loadaddr=10000\0" \ 92 "u-boot=u-boot.bin\0" \ 93 "load=tftp ${loadaddr) ${u-boot}\0" \ 94 "upd=run load; run prog\0" \ 95 "prog=prot off ffe00000 ffe3ffff;" \ 96 "era ffe00000 ffe3ffff;" \ 97 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 98 "save\0" \ 99 "" 100 101 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 102 103 #if defined(CONFIG_CMD_KGDB) 104 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 105 #else 106 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 107 #endif 108 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 112 #define CONFIG_SYS_LOAD_ADDR 0x20000 113 #define CONFIG_SYS_MEMTEST_START 0x400 114 #define CONFIG_SYS_MEMTEST_END 0x380000 115 #define CONFIG_SYS_CLK 66000000 116 117 /* 118 * Low Level Configuration Settings 119 * (address mappings, register initial values, etc.) 120 * You should know what you are doing if you make changes here. 121 */ 122 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 123 #define CONFIG_SYS_SCR 0x0003 124 #define CONFIG_SYS_SPR 0xffff 125 126 /*----------------------------------------------------------------------- 127 * Definitions for initial stack pointer and data area (in DPRAM) 128 */ 129 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 130 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 132 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 133 134 /*----------------------------------------------------------------------- 135 * Start addresses for the final memory configuration 136 * (Set up by the startup code) 137 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 138 */ 139 #define CONFIG_SYS_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 141 #define CONFIG_SYS_FLASH_BASE 0xffe00000 142 143 #ifdef CONFIG_MONITOR_IS_IN_RAM 144 #define CONFIG_SYS_MONITOR_BASE 0x20000 145 #else 146 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 147 #endif 148 149 #define CONFIG_SYS_MONITOR_LEN 0x20000 150 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 151 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 152 153 /* 154 * For booting Linux, the board info and command line data 155 * have to be in the first 8 MB of memory, since this is 156 * the maximum mapped by the Linux kernel during initialization ?? 157 */ 158 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 159 160 /* 161 * FLASH organization 162 */ 163 #define CONFIG_SYS_FLASH_CFI 164 #ifdef CONFIG_SYS_FLASH_CFI 165 # define CONFIG_FLASH_CFI_DRIVER 1 166 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 167 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 168 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 170 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 171 #endif 172 173 /*----------------------------------------------------------------------- 174 * Cache Configuration 175 */ 176 #define CONFIG_SYS_CACHELINE_SIZE 16 177 178 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 179 CONFIG_SYS_INIT_RAM_SIZE - 8) 180 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 181 CONFIG_SYS_INIT_RAM_SIZE - 4) 182 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 183 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 184 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 185 CF_ACR_EN | CF_ACR_SM_ALL) 186 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 187 CF_CACR_DISD | CF_CACR_INVI | \ 188 CF_CACR_CEIB | CF_CACR_DCM | \ 189 CF_CACR_EUSP) 190 191 /*----------------------------------------------------------------------- 192 * Memory bank definitions 193 */ 194 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 195 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 196 #define CONFIG_SYS_BR1_PRELIM 0 197 #define CONFIG_SYS_OR1_PRELIM 0 198 #define CONFIG_SYS_BR2_PRELIM 0x30000001 199 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 200 #define CONFIG_SYS_BR3_PRELIM 0 201 #define CONFIG_SYS_OR3_PRELIM 0 202 #define CONFIG_SYS_BR4_PRELIM 0 203 #define CONFIG_SYS_OR4_PRELIM 0 204 #define CONFIG_SYS_BR5_PRELIM 0 205 #define CONFIG_SYS_OR5_PRELIM 0 206 #define CONFIG_SYS_BR6_PRELIM 0 207 #define CONFIG_SYS_OR6_PRELIM 0 208 #define CONFIG_SYS_BR7_PRELIM 0x00000701 209 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C 210 211 /*----------------------------------------------------------------------- 212 * Port configuration 213 */ 214 #define CONFIG_SYS_PACNT 0x00000000 215 #define CONFIG_SYS_PADDR 0x0000 216 #define CONFIG_SYS_PADAT 0x0000 217 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 218 #define CONFIG_SYS_PBDDR 0x0000 219 #define CONFIG_SYS_PBDAT 0x0000 220 #define CONFIG_SYS_PDCNT 0x00000000 221 #endif /* _M5272C3_H */ 222