1 /* 2 * Configuation settings for the Motorola MC5272C3 board. 3 * 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * board/config.h - configuration options, board specific 27 */ 28 29 #ifndef _M5272C3_H 30 #define _M5272C3_H 31 32 /* 33 * High Level Configuration Options 34 * (easy to change) 35 */ 36 #define CONFIG_MCF52x2 /* define processor family */ 37 #define CONFIG_M5272 /* define processor type */ 38 39 #define CONFIG_MCFTMR 40 41 #define CONFIG_MCFUART 42 #define CFG_UART_PORT (0) 43 #define CONFIG_BAUDRATE 19200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 48 49 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 50 51 /* Configuration for environment 52 * Environment is embedded in u-boot in the second sector of the flash 53 */ 54 #ifndef CONFIG_MONITOR_IS_IN_RAM 55 #define CFG_ENV_OFFSET 0x4000 56 #define CFG_ENV_SECT_SIZE 0x2000 57 #define CFG_ENV_IS_IN_FLASH 1 58 #define CFG_ENV_IS_EMBEDDED 1 59 #else 60 #define CFG_ENV_ADDR 0xffe04000 61 #define CFG_ENV_SECT_SIZE 0x2000 62 #define CFG_ENV_IS_IN_FLASH 1 63 #endif 64 65 /* 66 * BOOTP options 67 */ 68 #define CONFIG_BOOTP_BOOTFILESIZE 69 #define CONFIG_BOOTP_BOOTPATH 70 #define CONFIG_BOOTP_GATEWAY 71 #define CONFIG_BOOTP_HOSTNAME 72 73 /* 74 * Command line configuration. 75 */ 76 #include <config_cmd_default.h> 77 78 #define CONFIG_CMD_MII 79 #define CONFIG_CMD_NET 80 #define CONFIG_CMD_PING 81 #define CONFIG_CMD_MISC 82 #define CONFIG_CMD_ELF 83 #define CONFIG_CMD_FLASH 84 #define CONFIG_CMD_MEMORY 85 86 #undef CONFIG_CMD_LOADS 87 #undef CONFIG_CMD_LOADB 88 89 #define CONFIG_BOOTDELAY 5 90 #define CONFIG_MCFFEC 91 #ifdef CONFIG_MCFFEC 92 # define CONFIG_NET_MULTI 1 93 # define CONFIG_MII 1 94 # define CFG_DISCOVER_PHY 95 # define CFG_RX_ETH_BUFFER 8 96 # define CFG_FAULT_ECHO_LINK_DOWN 97 98 # define CFG_FEC0_PINMUX 0 99 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 100 # define MCFFEC_TOUT_LOOP 50000 101 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 102 # ifndef CFG_DISCOVER_PHY 103 # define FECDUPLEX FULL 104 # define FECSPEED _100BASET 105 # else 106 # ifndef CFG_FAULT_ECHO_LINK_DOWN 107 # define CFG_FAULT_ECHO_LINK_DOWN 108 # endif 109 # endif /* CFG_DISCOVER_PHY */ 110 #endif 111 112 #ifdef CONFIG_MCFFEC 113 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 114 # define CONFIG_IPADDR 192.162.1.2 115 # define CONFIG_NETMASK 255.255.255.0 116 # define CONFIG_SERVERIP 192.162.1.1 117 # define CONFIG_GATEWAYIP 192.162.1.1 118 # define CONFIG_OVERWRITE_ETHADDR_ONCE 119 #endif /* CONFIG_MCFFEC */ 120 121 #define CONFIG_HOSTNAME M5272C3 122 #define CONFIG_EXTRA_ENV_SETTINGS \ 123 "netdev=eth0\0" \ 124 "loadaddr=10000\0" \ 125 "u-boot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr) ${u-boot}\0" \ 127 "upd=run load; run prog\0" \ 128 "prog=prot off ffe00000 ffe3ffff;" \ 129 "era ffe00000 ffe3ffff;" \ 130 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 131 "save\0" \ 132 "" 133 134 #define CFG_PROMPT "-> " 135 #define CFG_LONGHELP /* undef to save memory */ 136 137 #if defined(CONFIG_CMD_KGDB) 138 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 139 #else 140 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 141 #endif 142 143 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 144 #define CFG_MAXARGS 16 /* max number of command args */ 145 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 146 #define CFG_LOAD_ADDR 0x20000 147 #define CFG_MEMTEST_START 0x400 148 #define CFG_MEMTEST_END 0x380000 149 #define CFG_HZ 1000 150 #define CFG_CLK 66000000 151 152 /* 153 * Low Level Configuration Settings 154 * (address mappings, register initial values, etc.) 155 * You should know what you are doing if you make changes here. 156 */ 157 #define CFG_MBAR 0x10000000 /* Register Base Addrs */ 158 #define CFG_SCR 0x0003; 159 #define CFG_SPR 0xffff; 160 161 /*----------------------------------------------------------------------- 162 * Definitions for initial stack pointer and data area (in DPRAM) 163 */ 164 #define CFG_INIT_RAM_ADDR 0x20000000 165 #define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ 166 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 167 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 168 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 169 170 /*----------------------------------------------------------------------- 171 * Start addresses for the final memory configuration 172 * (Set up by the startup code) 173 * Please note that CFG_SDRAM_BASE _must_ start at 0 174 */ 175 #define CFG_SDRAM_BASE 0x00000000 176 #define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ 177 #define CFG_FLASH_BASE 0xffe00000 178 179 #ifdef CONFIG_MONITOR_IS_IN_RAM 180 #define CFG_MONITOR_BASE 0x20000 181 #else 182 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 183 #endif 184 185 #define CFG_MONITOR_LEN 0x20000 186 #define CFG_MALLOC_LEN (256 << 10) 187 #define CFG_BOOTPARAMS_LEN 64*1024 188 189 /* 190 * For booting Linux, the board info and command line data 191 * have to be in the first 8 MB of memory, since this is 192 * the maximum mapped by the Linux kernel during initialization ?? 193 */ 194 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 195 196 /*----------------------------------------------------------------------- 197 * FLASH organization 198 */ 199 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 200 #define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 201 #define CFG_FLASH_ERASE_TOUT 1000 202 203 /*----------------------------------------------------------------------- 204 * Cache Configuration 205 */ 206 #define CFG_CACHELINE_SIZE 16 207 208 /*----------------------------------------------------------------------- 209 * Memory bank definitions 210 */ 211 #define CFG_BR0_PRELIM 0xFFE00201 212 #define CFG_OR0_PRELIM 0xFFE00014 213 #define CFG_BR1_PRELIM 0 214 #define CFG_OR1_PRELIM 0 215 #define CFG_BR2_PRELIM 0x30000001 216 #define CFG_OR2_PRELIM 0xFFF80000 217 #define CFG_BR3_PRELIM 0 218 #define CFG_OR3_PRELIM 0 219 #define CFG_BR4_PRELIM 0 220 #define CFG_OR4_PRELIM 0 221 #define CFG_BR5_PRELIM 0 222 #define CFG_OR5_PRELIM 0 223 #define CFG_BR6_PRELIM 0 224 #define CFG_OR6_PRELIM 0 225 #define CFG_BR7_PRELIM 0x00000701 226 #define CFG_OR7_PRELIM 0xFFC0007C 227 228 /*----------------------------------------------------------------------- 229 * Port configuration 230 */ 231 #define CFG_PACNT 0x00000000 232 #define CFG_PADDR 0x0000 233 #define CFG_PADAT 0x0000 234 #define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ 235 #define CFG_PBDDR 0x0000 236 #define CFG_PBDAT 0x0000 237 #define CFG_PDCNT 0x00000000 238 #endif /* _M5272C3_H */ 239