1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_MCFTMR 11 12 #define CONFIG_MCFUART 13 #define CONFIG_SYS_UART_PORT (0) 14 15 #undef CONFIG_WATCHDOG /* disable watchdog */ 16 17 18 /* Configuration for environment 19 * Environment is embedded in u-boot in the second sector of the flash 20 */ 21 #ifdef CONFIG_MONITOR_IS_IN_RAM 22 # define CONFIG_ENV_OFFSET 0x4000 23 # define CONFIG_ENV_SECT_SIZE 0x1000 24 #else 25 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 26 # define CONFIG_ENV_SECT_SIZE 0x1000 27 #endif 28 29 #define LDS_BOARD_TEXT \ 30 . = DEFINED(env_offset) ? env_offset : .; \ 31 env/embedded.o(.text*); 32 33 /* 34 * Command line configuration. 35 */ 36 37 #ifdef CONFIG_IDE 38 /* ATA */ 39 # define CONFIG_IDE_RESET 1 40 # define CONFIG_IDE_PREINIT 1 41 # define CONFIG_ATAPI 42 # undef CONFIG_LBA48 43 44 # define CONFIG_SYS_IDE_MAXBUS 1 45 # define CONFIG_SYS_IDE_MAXDEVICE 2 46 47 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 48 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 49 50 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 51 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 52 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 53 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 54 #endif 55 56 #define CONFIG_DRIVER_DM9000 57 #ifdef CONFIG_DRIVER_DM9000 58 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 59 # define DM9000_IO CONFIG_DM9000_BASE 60 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 61 # undef CONFIG_DM9000_DEBUG 62 # define CONFIG_DM9000_BYTE_SWAPPED 63 64 # define CONFIG_OVERWRITE_ETHADDR_ONCE 65 66 # define CONFIG_EXTRA_ENV_SETTINGS \ 67 "netdev=eth0\0" \ 68 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 69 "loadaddr=10000\0" \ 70 "u-boot=u-boot.bin\0" \ 71 "load=tftp ${loadaddr) ${u-boot}\0" \ 72 "upd=run load; run prog\0" \ 73 "prog=prot off 0xff800000 0xff82ffff;" \ 74 "era 0xff800000 0xff82ffff;" \ 75 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 76 "save\0" \ 77 "" 78 #endif 79 80 #define CONFIG_HOSTNAME M5253DEMO 81 82 /* I2C */ 83 #define CONFIG_SYS_I2C 84 #define CONFIG_SYS_I2C_FSL 85 #define CONFIG_SYS_FSL_I2C_SPEED 80000 86 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 87 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 88 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 89 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 90 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 91 #define CONFIG_SYS_I2C_PINMUX_SET (0) 92 93 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 94 95 #define CONFIG_SYS_LOAD_ADDR 0x00100000 96 97 #define CONFIG_SYS_MEMTEST_START 0x400 98 #define CONFIG_SYS_MEMTEST_END 0x380000 99 100 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 101 #define CONFIG_SYS_FAST_CLK 102 #ifdef CONFIG_SYS_FAST_CLK 103 # define CONFIG_SYS_PLLCR 0x1243E054 104 # define CONFIG_SYS_CLK 140000000 105 #else 106 # define CONFIG_SYS_PLLCR 0x135a4140 107 # define CONFIG_SYS_CLK 70000000 108 #endif 109 110 /* 111 * Low Level Configuration Settings 112 * (address mappings, register initial values, etc.) 113 * You should know what you are doing if you make changes here. 114 */ 115 116 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 117 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 118 119 /* 120 * Definitions for initial stack pointer and data area (in DPRAM) 121 */ 122 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 123 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 124 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 125 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 126 127 /* 128 * Start addresses for the final memory configuration 129 * (Set up by the startup code) 130 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 131 */ 132 #define CONFIG_SYS_SDRAM_BASE 0x00000000 133 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 134 135 #ifdef CONFIG_MONITOR_IS_IN_RAM 136 # define CONFIG_SYS_MONITOR_BASE 0x20000 137 #else 138 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 139 #endif 140 141 #define CONFIG_SYS_MONITOR_LEN 0x40000 142 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 143 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 144 145 /* 146 * For booting Linux, the board info and command line data 147 * have to be in the first 8 MB of memory, since this is 148 * the maximum mapped by the Linux kernel during initialization ?? 149 */ 150 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 151 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 152 153 /* FLASH organization */ 154 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 155 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 156 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 158 159 #define FLASH_SST6401B 0x200 160 #define SST_ID_xF6401B 0x236D236D 161 162 #undef CONFIG_SYS_FLASH_CFI 163 #ifdef CONFIG_SYS_FLASH_CFI 164 /* 165 * Unable to use CFI driver, due to incompatible sector erase command by SST. 166 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 167 * 0x30 is block erase in SST 168 */ 169 # define CONFIG_FLASH_CFI_DRIVER 1 170 # define CONFIG_SYS_FLASH_SIZE 0x800000 171 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 172 # define CONFIG_FLASH_CFI_LEGACY 173 #else 174 # define CONFIG_SYS_SST_SECT 2048 175 # define CONFIG_SYS_SST_SECTSZ 0x1000 176 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 177 #endif 178 179 /* Cache Configuration */ 180 #define CONFIG_SYS_CACHELINE_SIZE 16 181 182 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 183 CONFIG_SYS_INIT_RAM_SIZE - 8) 184 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 185 CONFIG_SYS_INIT_RAM_SIZE - 4) 186 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 187 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 188 CF_ADDRMASK(8) | \ 189 CF_ACR_EN | CF_ACR_SM_ALL) 190 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 191 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 192 CF_ACR_EN | CF_ACR_SM_ALL) 193 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 194 CF_CACR_DBWE) 195 196 /* Port configuration */ 197 #define CONFIG_SYS_FECI2C 0xF0 198 199 #define CONFIG_SYS_CS0_BASE 0xFF800000 200 #define CONFIG_SYS_CS0_MASK 0x007F0021 201 #define CONFIG_SYS_CS0_CTRL 0x00001D80 202 203 #define CONFIG_SYS_CS1_BASE 0xE0000000 204 #define CONFIG_SYS_CS1_MASK 0x00000001 205 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 206 207 /*----------------------------------------------------------------------- 208 * Port configuration 209 */ 210 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 211 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 212 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 213 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 214 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 215 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 216 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 217 218 #endif /* _M5253DEMO_H */ 219