1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 #define CONFIG_BAUDRATE 115200 17 18 #undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 #define CONFIG_BOOTDELAY 5 21 22 /* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 #ifdef CONFIG_MONITOR_IS_IN_RAM 26 # define CONFIG_ENV_OFFSET 0x4000 27 # define CONFIG_ENV_SECT_SIZE 0x1000 28 # define CONFIG_ENV_IS_IN_FLASH 1 29 #else 30 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 31 # define CONFIG_ENV_SECT_SIZE 0x1000 32 # define CONFIG_ENV_IS_IN_FLASH 1 33 #endif 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text*); 38 39 /* 40 * Command line configuration. 41 */ 42 #define CONFIG_CMD_CACHE 43 #define CONFIG_CMD_EXT2 44 #define CONFIG_CMD_FAT 45 #define CONFIG_CMD_IDE 46 #define CONFIG_CMD_PING 47 48 #ifdef CONFIG_CMD_IDE 49 /* ATA */ 50 # define CONFIG_DOS_PARTITION 51 # define CONFIG_MAC_PARTITION 52 # define CONFIG_IDE_RESET 1 53 # define CONFIG_IDE_PREINIT 1 54 # define CONFIG_ATAPI 55 # undef CONFIG_LBA48 56 57 # define CONFIG_SYS_IDE_MAXBUS 1 58 # define CONFIG_SYS_IDE_MAXDEVICE 2 59 60 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 61 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 62 63 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 64 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 65 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 66 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 67 #endif 68 69 #define CONFIG_DRIVER_DM9000 70 #ifdef CONFIG_DRIVER_DM9000 71 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 72 # define DM9000_IO CONFIG_DM9000_BASE 73 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 74 # undef CONFIG_DM9000_DEBUG 75 # define CONFIG_DM9000_BYTE_SWAPPED 76 77 # define CONFIG_OVERWRITE_ETHADDR_ONCE 78 79 # define CONFIG_EXTRA_ENV_SETTINGS \ 80 "netdev=eth0\0" \ 81 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 82 "loadaddr=10000\0" \ 83 "u-boot=u-boot.bin\0" \ 84 "load=tftp ${loadaddr) ${u-boot}\0" \ 85 "upd=run load; run prog\0" \ 86 "prog=prot off 0xff800000 0xff82ffff;" \ 87 "era 0xff800000 0xff82ffff;" \ 88 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 89 "save\0" \ 90 "" 91 #endif 92 93 #define CONFIG_HOSTNAME M5253DEMO 94 95 /* I2C */ 96 #define CONFIG_SYS_I2C 97 #define CONFIG_SYS_I2C_FSL 98 #define CONFIG_SYS_FSL_I2C_SPEED 80000 99 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 100 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 101 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 102 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 103 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 104 #define CONFIG_SYS_I2C_PINMUX_SET (0) 105 106 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 107 108 #if defined(CONFIG_CMD_KGDB) 109 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 110 #else 111 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 112 #endif 113 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 114 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 115 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 116 117 #define CONFIG_SYS_LOAD_ADDR 0x00100000 118 119 #define CONFIG_SYS_MEMTEST_START 0x400 120 #define CONFIG_SYS_MEMTEST_END 0x380000 121 122 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 123 #define CONFIG_SYS_FAST_CLK 124 #ifdef CONFIG_SYS_FAST_CLK 125 # define CONFIG_SYS_PLLCR 0x1243E054 126 # define CONFIG_SYS_CLK 140000000 127 #else 128 # define CONFIG_SYS_PLLCR 0x135a4140 129 # define CONFIG_SYS_CLK 70000000 130 #endif 131 132 /* 133 * Low Level Configuration Settings 134 * (address mappings, register initial values, etc.) 135 * You should know what you are doing if you make changes here. 136 */ 137 138 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 139 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 140 141 /* 142 * Definitions for initial stack pointer and data area (in DPRAM) 143 */ 144 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 145 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 146 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 147 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 148 149 /* 150 * Start addresses for the final memory configuration 151 * (Set up by the startup code) 152 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 153 */ 154 #define CONFIG_SYS_SDRAM_BASE 0x00000000 155 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 156 157 #ifdef CONFIG_MONITOR_IS_IN_RAM 158 # define CONFIG_SYS_MONITOR_BASE 0x20000 159 #else 160 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 161 #endif 162 163 #define CONFIG_SYS_MONITOR_LEN 0x40000 164 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 165 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 166 167 /* 168 * For booting Linux, the board info and command line data 169 * have to be in the first 8 MB of memory, since this is 170 * the maximum mapped by the Linux kernel during initialization ?? 171 */ 172 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 173 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 174 175 /* FLASH organization */ 176 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 180 181 #define FLASH_SST6401B 0x200 182 #define SST_ID_xF6401B 0x236D236D 183 184 #undef CONFIG_SYS_FLASH_CFI 185 #ifdef CONFIG_SYS_FLASH_CFI 186 /* 187 * Unable to use CFI driver, due to incompatible sector erase command by SST. 188 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 189 * 0x30 is block erase in SST 190 */ 191 # define CONFIG_FLASH_CFI_DRIVER 1 192 # define CONFIG_SYS_FLASH_SIZE 0x800000 193 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 194 # define CONFIG_FLASH_CFI_LEGACY 195 #else 196 # define CONFIG_SYS_SST_SECT 2048 197 # define CONFIG_SYS_SST_SECTSZ 0x1000 198 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 199 #endif 200 201 /* Cache Configuration */ 202 #define CONFIG_SYS_CACHELINE_SIZE 16 203 204 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 205 CONFIG_SYS_INIT_RAM_SIZE - 8) 206 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 4) 208 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 209 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 210 CF_ADDRMASK(8) | \ 211 CF_ACR_EN | CF_ACR_SM_ALL) 212 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 213 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 214 CF_ACR_EN | CF_ACR_SM_ALL) 215 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 216 CF_CACR_DBWE) 217 218 /* Port configuration */ 219 #define CONFIG_SYS_FECI2C 0xF0 220 221 #define CONFIG_SYS_CS0_BASE 0xFF800000 222 #define CONFIG_SYS_CS0_MASK 0x007F0021 223 #define CONFIG_SYS_CS0_CTRL 0x00001D80 224 225 #define CONFIG_SYS_CS1_BASE 0xE0000000 226 #define CONFIG_SYS_CS1_MASK 0x00000001 227 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 228 229 /*----------------------------------------------------------------------- 230 * Port configuration 231 */ 232 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 233 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 234 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 235 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 236 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 237 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 238 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 239 240 #endif /* _M5253DEMO_H */ 241