1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 */ 5 6 #ifndef _M5253DEMO_H 7 #define _M5253DEMO_H 8 9 #define CONFIG_MCFTMR 10 11 #define CONFIG_MCFUART 12 #define CONFIG_SYS_UART_PORT (0) 13 14 #undef CONFIG_WATCHDOG /* disable watchdog */ 15 16 17 /* Configuration for environment 18 * Environment is embedded in u-boot in the second sector of the flash 19 */ 20 #ifdef CONFIG_MONITOR_IS_IN_RAM 21 # define CONFIG_ENV_OFFSET 0x4000 22 # define CONFIG_ENV_SECT_SIZE 0x1000 23 #else 24 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 25 # define CONFIG_ENV_SECT_SIZE 0x1000 26 #endif 27 28 #define LDS_BOARD_TEXT \ 29 . = DEFINED(env_offset) ? env_offset : .; \ 30 env/embedded.o(.text*); 31 32 /* 33 * Command line configuration. 34 */ 35 36 #ifdef CONFIG_IDE 37 /* ATA */ 38 # define CONFIG_IDE_RESET 1 39 # define CONFIG_IDE_PREINIT 1 40 # define CONFIG_ATAPI 41 # undef CONFIG_LBA48 42 43 # define CONFIG_SYS_IDE_MAXBUS 1 44 # define CONFIG_SYS_IDE_MAXDEVICE 2 45 46 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 47 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 48 49 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 50 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 51 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 52 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 53 #endif 54 55 #define CONFIG_DRIVER_DM9000 56 #ifdef CONFIG_DRIVER_DM9000 57 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 58 # define DM9000_IO CONFIG_DM9000_BASE 59 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 60 # undef CONFIG_DM9000_DEBUG 61 # define CONFIG_DM9000_BYTE_SWAPPED 62 63 # define CONFIG_OVERWRITE_ETHADDR_ONCE 64 65 # define CONFIG_EXTRA_ENV_SETTINGS \ 66 "netdev=eth0\0" \ 67 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 68 "loadaddr=10000\0" \ 69 "u-boot=u-boot.bin\0" \ 70 "load=tftp ${loadaddr) ${u-boot}\0" \ 71 "upd=run load; run prog\0" \ 72 "prog=prot off 0xff800000 0xff82ffff;" \ 73 "era 0xff800000 0xff82ffff;" \ 74 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 75 "save\0" \ 76 "" 77 #endif 78 79 #define CONFIG_HOSTNAME "M5253DEMO" 80 81 /* I2C */ 82 #define CONFIG_SYS_I2C 83 #define CONFIG_SYS_I2C_FSL 84 #define CONFIG_SYS_FSL_I2C_SPEED 80000 85 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 86 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 87 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 88 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 89 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 90 #define CONFIG_SYS_I2C_PINMUX_SET (0) 91 92 #define CONFIG_SYS_LOAD_ADDR 0x00100000 93 94 #define CONFIG_SYS_MEMTEST_START 0x400 95 #define CONFIG_SYS_MEMTEST_END 0x380000 96 97 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 98 #define CONFIG_SYS_FAST_CLK 99 #ifdef CONFIG_SYS_FAST_CLK 100 # define CONFIG_SYS_PLLCR 0x1243E054 101 # define CONFIG_SYS_CLK 140000000 102 #else 103 # define CONFIG_SYS_PLLCR 0x135a4140 104 # define CONFIG_SYS_CLK 70000000 105 #endif 106 107 /* 108 * Low Level Configuration Settings 109 * (address mappings, register initial values, etc.) 110 * You should know what you are doing if you make changes here. 111 */ 112 113 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 114 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 115 116 /* 117 * Definitions for initial stack pointer and data area (in DPRAM) 118 */ 119 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 120 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 121 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 122 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 123 124 /* 125 * Start addresses for the final memory configuration 126 * (Set up by the startup code) 127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 128 */ 129 #define CONFIG_SYS_SDRAM_BASE 0x00000000 130 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 131 132 #ifdef CONFIG_MONITOR_IS_IN_RAM 133 # define CONFIG_SYS_MONITOR_BASE 0x20000 134 #else 135 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 136 #endif 137 138 #define CONFIG_SYS_MONITOR_LEN 0x40000 139 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 140 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 141 142 /* 143 * For booting Linux, the board info and command line data 144 * have to be in the first 8 MB of memory, since this is 145 * the maximum mapped by the Linux kernel during initialization ?? 146 */ 147 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 148 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 149 150 /* FLASH organization */ 151 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 153 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 154 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 155 156 #define FLASH_SST6401B 0x200 157 #define SST_ID_xF6401B 0x236D236D 158 159 #undef CONFIG_SYS_FLASH_CFI 160 #ifdef CONFIG_SYS_FLASH_CFI 161 /* 162 * Unable to use CFI driver, due to incompatible sector erase command by SST. 163 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 164 * 0x30 is block erase in SST 165 */ 166 # define CONFIG_FLASH_CFI_DRIVER 1 167 # define CONFIG_SYS_FLASH_SIZE 0x800000 168 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 169 # define CONFIG_FLASH_CFI_LEGACY 170 #else 171 # define CONFIG_SYS_SST_SECT 2048 172 # define CONFIG_SYS_SST_SECTSZ 0x1000 173 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 174 #endif 175 176 /* Cache Configuration */ 177 #define CONFIG_SYS_CACHELINE_SIZE 16 178 179 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 180 CONFIG_SYS_INIT_RAM_SIZE - 8) 181 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 182 CONFIG_SYS_INIT_RAM_SIZE - 4) 183 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 184 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 185 CF_ADDRMASK(8) | \ 186 CF_ACR_EN | CF_ACR_SM_ALL) 187 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 188 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 189 CF_ACR_EN | CF_ACR_SM_ALL) 190 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 191 CF_CACR_DBWE) 192 193 /* Port configuration */ 194 #define CONFIG_SYS_FECI2C 0xF0 195 196 #define CONFIG_SYS_CS0_BASE 0xFF800000 197 #define CONFIG_SYS_CS0_MASK 0x007F0021 198 #define CONFIG_SYS_CS0_CTRL 0x00001D80 199 200 #define CONFIG_SYS_CS1_BASE 0xE0000000 201 #define CONFIG_SYS_CS1_MASK 0x00000001 202 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 203 204 /*----------------------------------------------------------------------- 205 * Port configuration 206 */ 207 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 208 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 209 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 210 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 211 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 212 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 213 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 214 215 #endif /* _M5253DEMO_H */ 216