1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 17 #undef CONFIG_WATCHDOG /* disable watchdog */ 18 19 20 /* Configuration for environment 21 * Environment is embedded in u-boot in the second sector of the flash 22 */ 23 #ifdef CONFIG_MONITOR_IS_IN_RAM 24 # define CONFIG_ENV_OFFSET 0x4000 25 # define CONFIG_ENV_SECT_SIZE 0x1000 26 # define CONFIG_ENV_IS_IN_FLASH 1 27 #else 28 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 29 # define CONFIG_ENV_SECT_SIZE 0x1000 30 # define CONFIG_ENV_IS_IN_FLASH 1 31 #endif 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 common/env_embedded.o (.text*); 36 37 /* 38 * Command line configuration. 39 */ 40 41 #ifdef CONFIG_IDE 42 /* ATA */ 43 # define CONFIG_IDE_RESET 1 44 # define CONFIG_IDE_PREINIT 1 45 # define CONFIG_ATAPI 46 # undef CONFIG_LBA48 47 48 # define CONFIG_SYS_IDE_MAXBUS 1 49 # define CONFIG_SYS_IDE_MAXDEVICE 2 50 51 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 52 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 53 54 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 55 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 56 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 57 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 58 #endif 59 60 #define CONFIG_DRIVER_DM9000 61 #ifdef CONFIG_DRIVER_DM9000 62 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 63 # define DM9000_IO CONFIG_DM9000_BASE 64 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 65 # undef CONFIG_DM9000_DEBUG 66 # define CONFIG_DM9000_BYTE_SWAPPED 67 68 # define CONFIG_OVERWRITE_ETHADDR_ONCE 69 70 # define CONFIG_EXTRA_ENV_SETTINGS \ 71 "netdev=eth0\0" \ 72 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 73 "loadaddr=10000\0" \ 74 "u-boot=u-boot.bin\0" \ 75 "load=tftp ${loadaddr) ${u-boot}\0" \ 76 "upd=run load; run prog\0" \ 77 "prog=prot off 0xff800000 0xff82ffff;" \ 78 "era 0xff800000 0xff82ffff;" \ 79 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 80 "save\0" \ 81 "" 82 #endif 83 84 #define CONFIG_HOSTNAME M5253DEMO 85 86 /* I2C */ 87 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_I2C_FSL 89 #define CONFIG_SYS_FSL_I2C_SPEED 80000 90 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 91 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 92 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 93 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 94 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 95 #define CONFIG_SYS_I2C_PINMUX_SET (0) 96 97 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 98 99 #if defined(CONFIG_CMD_KGDB) 100 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 101 #else 102 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 103 #endif 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 105 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 106 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 107 108 #define CONFIG_SYS_LOAD_ADDR 0x00100000 109 110 #define CONFIG_SYS_MEMTEST_START 0x400 111 #define CONFIG_SYS_MEMTEST_END 0x380000 112 113 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 114 #define CONFIG_SYS_FAST_CLK 115 #ifdef CONFIG_SYS_FAST_CLK 116 # define CONFIG_SYS_PLLCR 0x1243E054 117 # define CONFIG_SYS_CLK 140000000 118 #else 119 # define CONFIG_SYS_PLLCR 0x135a4140 120 # define CONFIG_SYS_CLK 70000000 121 #endif 122 123 /* 124 * Low Level Configuration Settings 125 * (address mappings, register initial values, etc.) 126 * You should know what you are doing if you make changes here. 127 */ 128 129 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 130 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 131 132 /* 133 * Definitions for initial stack pointer and data area (in DPRAM) 134 */ 135 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 136 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 137 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 138 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 139 140 /* 141 * Start addresses for the final memory configuration 142 * (Set up by the startup code) 143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 144 */ 145 #define CONFIG_SYS_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 147 148 #ifdef CONFIG_MONITOR_IS_IN_RAM 149 # define CONFIG_SYS_MONITOR_BASE 0x20000 150 #else 151 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 152 #endif 153 154 #define CONFIG_SYS_MONITOR_LEN 0x40000 155 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 156 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 157 158 /* 159 * For booting Linux, the board info and command line data 160 * have to be in the first 8 MB of memory, since this is 161 * the maximum mapped by the Linux kernel during initialization ?? 162 */ 163 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 164 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 165 166 /* FLASH organization */ 167 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 171 172 #define FLASH_SST6401B 0x200 173 #define SST_ID_xF6401B 0x236D236D 174 175 #undef CONFIG_SYS_FLASH_CFI 176 #ifdef CONFIG_SYS_FLASH_CFI 177 /* 178 * Unable to use CFI driver, due to incompatible sector erase command by SST. 179 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 180 * 0x30 is block erase in SST 181 */ 182 # define CONFIG_FLASH_CFI_DRIVER 1 183 # define CONFIG_SYS_FLASH_SIZE 0x800000 184 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 185 # define CONFIG_FLASH_CFI_LEGACY 186 #else 187 # define CONFIG_SYS_SST_SECT 2048 188 # define CONFIG_SYS_SST_SECTSZ 0x1000 189 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 190 #endif 191 192 /* Cache Configuration */ 193 #define CONFIG_SYS_CACHELINE_SIZE 16 194 195 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 196 CONFIG_SYS_INIT_RAM_SIZE - 8) 197 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 198 CONFIG_SYS_INIT_RAM_SIZE - 4) 199 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 200 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 201 CF_ADDRMASK(8) | \ 202 CF_ACR_EN | CF_ACR_SM_ALL) 203 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 204 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 205 CF_ACR_EN | CF_ACR_SM_ALL) 206 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 207 CF_CACR_DBWE) 208 209 /* Port configuration */ 210 #define CONFIG_SYS_FECI2C 0xF0 211 212 #define CONFIG_SYS_CS0_BASE 0xFF800000 213 #define CONFIG_SYS_CS0_MASK 0x007F0021 214 #define CONFIG_SYS_CS0_CTRL 0x00001D80 215 216 #define CONFIG_SYS_CS1_BASE 0xE0000000 217 #define CONFIG_SYS_CS1_MASK 0x00000001 218 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 219 220 /*----------------------------------------------------------------------- 221 * Port configuration 222 */ 223 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 224 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 225 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 226 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 227 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 228 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 229 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 230 231 #endif /* _M5253DEMO_H */ 232