1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 #define CONFIG_BAUDRATE 115200 17 18 #undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 #define CONFIG_BOOTDELAY 5 21 22 /* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 #ifdef CONFIG_MONITOR_IS_IN_RAM 26 # define CONFIG_ENV_OFFSET 0x4000 27 # define CONFIG_ENV_SECT_SIZE 0x1000 28 # define CONFIG_ENV_IS_IN_FLASH 1 29 #else 30 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 31 # define CONFIG_ENV_SECT_SIZE 0x1000 32 # define CONFIG_ENV_IS_IN_FLASH 1 33 #endif 34 35 #define LDS_BOARD_TEXT \ 36 . = DEFINED(env_offset) ? env_offset : .; \ 37 common/env_embedded.o (.text*); 38 39 /* 40 * Command line configuration. 41 */ 42 #include <config_cmd_default.h> 43 44 #define CONFIG_CMD_CACHE 45 #define CONFIG_CMD_LOADB 46 #define CONFIG_CMD_LOADS 47 #define CONFIG_CMD_EXT2 48 #define CONFIG_CMD_FAT 49 #define CONFIG_CMD_IDE 50 #define CONFIG_CMD_MEMORY 51 #define CONFIG_CMD_MISC 52 #define CONFIG_CMD_PING 53 54 #ifdef CONFIG_CMD_IDE 55 /* ATA */ 56 # define CONFIG_DOS_PARTITION 57 # define CONFIG_MAC_PARTITION 58 # define CONFIG_IDE_RESET 1 59 # define CONFIG_IDE_PREINIT 1 60 # define CONFIG_ATAPI 61 # undef CONFIG_LBA48 62 63 # define CONFIG_SYS_IDE_MAXBUS 1 64 # define CONFIG_SYS_IDE_MAXDEVICE 2 65 66 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 67 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 68 69 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 70 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 71 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 72 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 73 #endif 74 75 #define CONFIG_DRIVER_DM9000 76 #ifdef CONFIG_DRIVER_DM9000 77 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 78 # define DM9000_IO CONFIG_DM9000_BASE 79 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 80 # undef CONFIG_DM9000_DEBUG 81 # define CONFIG_DM9000_BYTE_SWAPPED 82 83 # define CONFIG_OVERWRITE_ETHADDR_ONCE 84 85 # define CONFIG_EXTRA_ENV_SETTINGS \ 86 "netdev=eth0\0" \ 87 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 88 "loadaddr=10000\0" \ 89 "u-boot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr) ${u-boot}\0" \ 91 "upd=run load; run prog\0" \ 92 "prog=prot off 0xff800000 0xff82ffff;" \ 93 "era 0xff800000 0xff82ffff;" \ 94 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 95 "save\0" \ 96 "" 97 #endif 98 99 #define CONFIG_HOSTNAME M5253DEMO 100 101 /* I2C */ 102 #define CONFIG_SYS_I2C 103 #define CONFIG_SYS_I2C_FSL 104 #define CONFIG_SYS_FSL_I2C_SPEED 80000 105 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 106 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 107 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 108 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 109 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 110 #define CONFIG_SYS_I2C_PINMUX_SET (0) 111 112 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 113 114 #if defined(CONFIG_CMD_KGDB) 115 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 116 #else 117 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 118 #endif 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 120 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 121 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 122 123 #define CONFIG_SYS_LOAD_ADDR 0x00100000 124 125 #define CONFIG_SYS_MEMTEST_START 0x400 126 #define CONFIG_SYS_MEMTEST_END 0x380000 127 128 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 129 #define CONFIG_SYS_FAST_CLK 130 #ifdef CONFIG_SYS_FAST_CLK 131 # define CONFIG_SYS_PLLCR 0x1243E054 132 # define CONFIG_SYS_CLK 140000000 133 #else 134 # define CONFIG_SYS_PLLCR 0x135a4140 135 # define CONFIG_SYS_CLK 70000000 136 #endif 137 138 /* 139 * Low Level Configuration Settings 140 * (address mappings, register initial values, etc.) 141 * You should know what you are doing if you make changes here. 142 */ 143 144 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 145 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 146 147 /* 148 * Definitions for initial stack pointer and data area (in DPRAM) 149 */ 150 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 152 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 155 /* 156 * Start addresses for the final memory configuration 157 * (Set up by the startup code) 158 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 159 */ 160 #define CONFIG_SYS_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 162 163 #ifdef CONFIG_MONITOR_IS_IN_RAM 164 # define CONFIG_SYS_MONITOR_BASE 0x20000 165 #else 166 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 167 #endif 168 169 #define CONFIG_SYS_MONITOR_LEN 0x40000 170 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 171 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 172 173 /* 174 * For booting Linux, the board info and command line data 175 * have to be in the first 8 MB of memory, since this is 176 * the maximum mapped by the Linux kernel during initialization ?? 177 */ 178 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 179 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 180 181 /* FLASH organization */ 182 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 183 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 185 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 186 187 #define FLASH_SST6401B 0x200 188 #define SST_ID_xF6401B 0x236D236D 189 190 #undef CONFIG_SYS_FLASH_CFI 191 #ifdef CONFIG_SYS_FLASH_CFI 192 /* 193 * Unable to use CFI driver, due to incompatible sector erase command by SST. 194 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 195 * 0x30 is block erase in SST 196 */ 197 # define CONFIG_FLASH_CFI_DRIVER 1 198 # define CONFIG_SYS_FLASH_SIZE 0x800000 199 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 200 # define CONFIG_FLASH_CFI_LEGACY 201 #else 202 # define CONFIG_SYS_SST_SECT 2048 203 # define CONFIG_SYS_SST_SECTSZ 0x1000 204 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 205 #endif 206 207 /* Cache Configuration */ 208 #define CONFIG_SYS_CACHELINE_SIZE 16 209 210 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 211 CONFIG_SYS_INIT_RAM_SIZE - 8) 212 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 213 CONFIG_SYS_INIT_RAM_SIZE - 4) 214 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 215 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 216 CF_ADDRMASK(8) | \ 217 CF_ACR_EN | CF_ACR_SM_ALL) 218 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 219 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 220 CF_ACR_EN | CF_ACR_SM_ALL) 221 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 222 CF_CACR_DBWE) 223 224 /* Port configuration */ 225 #define CONFIG_SYS_FECI2C 0xF0 226 227 #define CONFIG_SYS_CS0_BASE 0xFF800000 228 #define CONFIG_SYS_CS0_MASK 0x007F0021 229 #define CONFIG_SYS_CS0_CTRL 0x00001D80 230 231 #define CONFIG_SYS_CS1_BASE 0xE0000000 232 #define CONFIG_SYS_CS1_MASK 0x00000001 233 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 234 235 /*----------------------------------------------------------------------- 236 * Port configuration 237 */ 238 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 239 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 240 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 241 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 242 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 243 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 244 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 245 246 #endif /* _M5253DEMO_H */ 247