1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_MCFTMR 11 12 #define CONFIG_MCFUART 13 #define CONFIG_SYS_UART_PORT (0) 14 15 #undef CONFIG_WATCHDOG /* disable watchdog */ 16 17 18 /* Configuration for environment 19 * Environment is embedded in u-boot in the second sector of the flash 20 */ 21 #ifdef CONFIG_MONITOR_IS_IN_RAM 22 # define CONFIG_ENV_OFFSET 0x4000 23 # define CONFIG_ENV_SECT_SIZE 0x1000 24 #else 25 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 26 # define CONFIG_ENV_SECT_SIZE 0x1000 27 #endif 28 29 #define LDS_BOARD_TEXT \ 30 . = DEFINED(env_offset) ? env_offset : .; \ 31 env/embedded.o(.text*); 32 33 /* 34 * Command line configuration. 35 */ 36 37 #ifdef CONFIG_IDE 38 /* ATA */ 39 # define CONFIG_IDE_RESET 1 40 # define CONFIG_IDE_PREINIT 1 41 # define CONFIG_ATAPI 42 # undef CONFIG_LBA48 43 44 # define CONFIG_SYS_IDE_MAXBUS 1 45 # define CONFIG_SYS_IDE_MAXDEVICE 2 46 47 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 48 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 49 50 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 51 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 52 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 53 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 54 #endif 55 56 #define CONFIG_DRIVER_DM9000 57 #ifdef CONFIG_DRIVER_DM9000 58 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 59 # define DM9000_IO CONFIG_DM9000_BASE 60 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 61 # undef CONFIG_DM9000_DEBUG 62 # define CONFIG_DM9000_BYTE_SWAPPED 63 64 # define CONFIG_OVERWRITE_ETHADDR_ONCE 65 66 # define CONFIG_EXTRA_ENV_SETTINGS \ 67 "netdev=eth0\0" \ 68 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 69 "loadaddr=10000\0" \ 70 "u-boot=u-boot.bin\0" \ 71 "load=tftp ${loadaddr) ${u-boot}\0" \ 72 "upd=run load; run prog\0" \ 73 "prog=prot off 0xff800000 0xff82ffff;" \ 74 "era 0xff800000 0xff82ffff;" \ 75 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 76 "save\0" \ 77 "" 78 #endif 79 80 #define CONFIG_HOSTNAME "M5253DEMO" 81 82 /* I2C */ 83 #define CONFIG_SYS_I2C 84 #define CONFIG_SYS_I2C_FSL 85 #define CONFIG_SYS_FSL_I2C_SPEED 80000 86 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 87 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 88 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 89 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 90 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 91 #define CONFIG_SYS_I2C_PINMUX_SET (0) 92 93 #define CONFIG_SYS_LOAD_ADDR 0x00100000 94 95 #define CONFIG_SYS_MEMTEST_START 0x400 96 #define CONFIG_SYS_MEMTEST_END 0x380000 97 98 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 99 #define CONFIG_SYS_FAST_CLK 100 #ifdef CONFIG_SYS_FAST_CLK 101 # define CONFIG_SYS_PLLCR 0x1243E054 102 # define CONFIG_SYS_CLK 140000000 103 #else 104 # define CONFIG_SYS_PLLCR 0x135a4140 105 # define CONFIG_SYS_CLK 70000000 106 #endif 107 108 /* 109 * Low Level Configuration Settings 110 * (address mappings, register initial values, etc.) 111 * You should know what you are doing if you make changes here. 112 */ 113 114 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 115 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 116 117 /* 118 * Definitions for initial stack pointer and data area (in DPRAM) 119 */ 120 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 121 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 122 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 123 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 124 125 /* 126 * Start addresses for the final memory configuration 127 * (Set up by the startup code) 128 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 129 */ 130 #define CONFIG_SYS_SDRAM_BASE 0x00000000 131 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 132 133 #ifdef CONFIG_MONITOR_IS_IN_RAM 134 # define CONFIG_SYS_MONITOR_BASE 0x20000 135 #else 136 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 137 #endif 138 139 #define CONFIG_SYS_MONITOR_LEN 0x40000 140 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 141 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 142 143 /* 144 * For booting Linux, the board info and command line data 145 * have to be in the first 8 MB of memory, since this is 146 * the maximum mapped by the Linux kernel during initialization ?? 147 */ 148 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 149 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 150 151 /* FLASH organization */ 152 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 154 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 155 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 156 157 #define FLASH_SST6401B 0x200 158 #define SST_ID_xF6401B 0x236D236D 159 160 #undef CONFIG_SYS_FLASH_CFI 161 #ifdef CONFIG_SYS_FLASH_CFI 162 /* 163 * Unable to use CFI driver, due to incompatible sector erase command by SST. 164 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 165 * 0x30 is block erase in SST 166 */ 167 # define CONFIG_FLASH_CFI_DRIVER 1 168 # define CONFIG_SYS_FLASH_SIZE 0x800000 169 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 170 # define CONFIG_FLASH_CFI_LEGACY 171 #else 172 # define CONFIG_SYS_SST_SECT 2048 173 # define CONFIG_SYS_SST_SECTSZ 0x1000 174 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 175 #endif 176 177 /* Cache Configuration */ 178 #define CONFIG_SYS_CACHELINE_SIZE 16 179 180 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 181 CONFIG_SYS_INIT_RAM_SIZE - 8) 182 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 183 CONFIG_SYS_INIT_RAM_SIZE - 4) 184 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 185 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 186 CF_ADDRMASK(8) | \ 187 CF_ACR_EN | CF_ACR_SM_ALL) 188 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 189 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 190 CF_ACR_EN | CF_ACR_SM_ALL) 191 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 192 CF_CACR_DBWE) 193 194 /* Port configuration */ 195 #define CONFIG_SYS_FECI2C 0xF0 196 197 #define CONFIG_SYS_CS0_BASE 0xFF800000 198 #define CONFIG_SYS_CS0_MASK 0x007F0021 199 #define CONFIG_SYS_CS0_CTRL 0x00001D80 200 201 #define CONFIG_SYS_CS1_BASE 0xE0000000 202 #define CONFIG_SYS_CS1_MASK 0x00000001 203 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 204 205 /*----------------------------------------------------------------------- 206 * Port configuration 207 */ 208 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 209 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 210 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 211 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 212 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 213 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 214 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 215 216 #endif /* _M5253DEMO_H */ 217