1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 #define CONFIG_BAUDRATE 115200 17 18 #undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 #define CONFIG_BOOTDELAY 5 21 22 /* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 #ifdef CONFIG_MONITOR_IS_IN_RAM 26 # define CONFIG_ENV_OFFSET 0x4000 27 # define CONFIG_ENV_SECT_SIZE 0x1000 28 # define CONFIG_ENV_IS_IN_FLASH 1 29 #else 30 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 31 # define CONFIG_ENV_SECT_SIZE 0x1000 32 # define CONFIG_ENV_IS_IN_FLASH 1 33 #endif 34 35 /* 36 * Command line configuration. 37 */ 38 #include <config_cmd_default.h> 39 40 #define CONFIG_CMD_CACHE 41 #define CONFIG_CMD_LOADB 42 #define CONFIG_CMD_LOADS 43 #define CONFIG_CMD_EXT2 44 #define CONFIG_CMD_FAT 45 #define CONFIG_CMD_IDE 46 #define CONFIG_CMD_MEMORY 47 #define CONFIG_CMD_MISC 48 #define CONFIG_CMD_PING 49 50 #ifdef CONFIG_CMD_IDE 51 /* ATA */ 52 # define CONFIG_DOS_PARTITION 53 # define CONFIG_MAC_PARTITION 54 # define CONFIG_IDE_RESET 1 55 # define CONFIG_IDE_PREINIT 1 56 # define CONFIG_ATAPI 57 # undef CONFIG_LBA48 58 59 # define CONFIG_SYS_IDE_MAXBUS 1 60 # define CONFIG_SYS_IDE_MAXDEVICE 2 61 62 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 63 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 64 65 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 66 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 67 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 68 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 69 #endif 70 71 #define CONFIG_DRIVER_DM9000 72 #ifdef CONFIG_DRIVER_DM9000 73 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 74 # define DM9000_IO CONFIG_DM9000_BASE 75 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 76 # undef CONFIG_DM9000_DEBUG 77 # define CONFIG_DM9000_BYTE_SWAPPED 78 79 # define CONFIG_OVERWRITE_ETHADDR_ONCE 80 81 # define CONFIG_EXTRA_ENV_SETTINGS \ 82 "netdev=eth0\0" \ 83 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 84 "loadaddr=10000\0" \ 85 "u-boot=u-boot.bin\0" \ 86 "load=tftp ${loadaddr) ${u-boot}\0" \ 87 "upd=run load; run prog\0" \ 88 "prog=prot off 0xff800000 0xff82ffff;" \ 89 "era 0xff800000 0xff82ffff;" \ 90 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 91 "save\0" \ 92 "" 93 #endif 94 95 #define CONFIG_HOSTNAME M5253DEMO 96 97 /* I2C */ 98 #define CONFIG_SYS_I2C 99 #define CONFIG_SYS_I2C_FSL 100 #define CONFIG_SYS_FSL_I2C_SPEED 80000 101 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 102 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 103 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 104 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 105 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 106 #define CONFIG_SYS_I2C_PINMUX_SET (0) 107 108 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 109 110 #if defined(CONFIG_CMD_KGDB) 111 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 112 #else 113 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 114 #endif 115 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 116 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 118 119 #define CONFIG_SYS_LOAD_ADDR 0x00100000 120 121 #define CONFIG_SYS_MEMTEST_START 0x400 122 #define CONFIG_SYS_MEMTEST_END 0x380000 123 124 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 125 #define CONFIG_SYS_FAST_CLK 126 #ifdef CONFIG_SYS_FAST_CLK 127 # define CONFIG_SYS_PLLCR 0x1243E054 128 # define CONFIG_SYS_CLK 140000000 129 #else 130 # define CONFIG_SYS_PLLCR 0x135a4140 131 # define CONFIG_SYS_CLK 70000000 132 #endif 133 134 /* 135 * Low Level Configuration Settings 136 * (address mappings, register initial values, etc.) 137 * You should know what you are doing if you make changes here. 138 */ 139 140 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 141 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 142 143 /* 144 * Definitions for initial stack pointer and data area (in DPRAM) 145 */ 146 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 147 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 148 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 149 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 150 151 /* 152 * Start addresses for the final memory configuration 153 * (Set up by the startup code) 154 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 155 */ 156 #define CONFIG_SYS_SDRAM_BASE 0x00000000 157 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 158 159 #ifdef CONFIG_MONITOR_IS_IN_RAM 160 # define CONFIG_SYS_MONITOR_BASE 0x20000 161 #else 162 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 163 #endif 164 165 #define CONFIG_SYS_MONITOR_LEN 0x40000 166 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 167 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 168 169 /* 170 * For booting Linux, the board info and command line data 171 * have to be in the first 8 MB of memory, since this is 172 * the maximum mapped by the Linux kernel during initialization ?? 173 */ 174 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 175 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 176 177 /* FLASH organization */ 178 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 179 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 180 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 181 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 182 183 #define FLASH_SST6401B 0x200 184 #define SST_ID_xF6401B 0x236D236D 185 186 #undef CONFIG_SYS_FLASH_CFI 187 #ifdef CONFIG_SYS_FLASH_CFI 188 /* 189 * Unable to use CFI driver, due to incompatible sector erase command by SST. 190 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 191 * 0x30 is block erase in SST 192 */ 193 # define CONFIG_FLASH_CFI_DRIVER 1 194 # define CONFIG_SYS_FLASH_SIZE 0x800000 195 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 196 # define CONFIG_FLASH_CFI_LEGACY 197 #else 198 # define CONFIG_SYS_SST_SECT 2048 199 # define CONFIG_SYS_SST_SECTSZ 0x1000 200 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 201 #endif 202 203 /* Cache Configuration */ 204 #define CONFIG_SYS_CACHELINE_SIZE 16 205 206 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 8) 208 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - 4) 210 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 211 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 212 CF_ADDRMASK(8) | \ 213 CF_ACR_EN | CF_ACR_SM_ALL) 214 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 215 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 216 CF_ACR_EN | CF_ACR_SM_ALL) 217 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 218 CF_CACR_DBWE) 219 220 /* Port configuration */ 221 #define CONFIG_SYS_FECI2C 0xF0 222 223 #define CONFIG_SYS_CS0_BASE 0xFF800000 224 #define CONFIG_SYS_CS0_MASK 0x007F0021 225 #define CONFIG_SYS_CS0_CTRL 0x00001D80 226 227 #define CONFIG_SYS_CS1_BASE 0xE0000000 228 #define CONFIG_SYS_CS1_MASK 0x00000001 229 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 230 231 /*----------------------------------------------------------------------- 232 * Port configuration 233 */ 234 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 235 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 236 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 237 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 238 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 239 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 240 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 241 242 #endif /* _M5253DEMO_H */ 243