1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 2 * Hayden Fraser (Hayden.Fraser@freescale.com) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _M5253DEMO_H 8 #define _M5253DEMO_H 9 10 #define CONFIG_M5253DEMO /* define board type */ 11 12 #define CONFIG_MCFTMR 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT (0) 16 17 #undef CONFIG_WATCHDOG /* disable watchdog */ 18 19 20 /* Configuration for environment 21 * Environment is embedded in u-boot in the second sector of the flash 22 */ 23 #ifdef CONFIG_MONITOR_IS_IN_RAM 24 # define CONFIG_ENV_OFFSET 0x4000 25 # define CONFIG_ENV_SECT_SIZE 0x1000 26 # define CONFIG_ENV_IS_IN_FLASH 1 27 #else 28 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 29 # define CONFIG_ENV_SECT_SIZE 0x1000 30 # define CONFIG_ENV_IS_IN_FLASH 1 31 #endif 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 common/env_embedded.o (.text*); 36 37 /* 38 * Command line configuration. 39 */ 40 #define CONFIG_CMD_IDE 41 42 #ifdef CONFIG_CMD_IDE 43 /* ATA */ 44 # define CONFIG_IDE_RESET 1 45 # define CONFIG_IDE_PREINIT 1 46 # define CONFIG_ATAPI 47 # undef CONFIG_LBA48 48 49 # define CONFIG_SYS_IDE_MAXBUS 1 50 # define CONFIG_SYS_IDE_MAXDEVICE 2 51 52 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 53 # define CONFIG_SYS_ATA_IDE0_OFFSET 0 54 55 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 56 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 57 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 58 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 59 #endif 60 61 #define CONFIG_DRIVER_DM9000 62 #ifdef CONFIG_DRIVER_DM9000 63 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 64 # define DM9000_IO CONFIG_DM9000_BASE 65 # define DM9000_DATA (CONFIG_DM9000_BASE + 4) 66 # undef CONFIG_DM9000_DEBUG 67 # define CONFIG_DM9000_BYTE_SWAPPED 68 69 # define CONFIG_OVERWRITE_ETHADDR_ONCE 70 71 # define CONFIG_EXTRA_ENV_SETTINGS \ 72 "netdev=eth0\0" \ 73 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 74 "loadaddr=10000\0" \ 75 "u-boot=u-boot.bin\0" \ 76 "load=tftp ${loadaddr) ${u-boot}\0" \ 77 "upd=run load; run prog\0" \ 78 "prog=prot off 0xff800000 0xff82ffff;" \ 79 "era 0xff800000 0xff82ffff;" \ 80 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 81 "save\0" \ 82 "" 83 #endif 84 85 #define CONFIG_HOSTNAME M5253DEMO 86 87 /* I2C */ 88 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_I2C_FSL 90 #define CONFIG_SYS_FSL_I2C_SPEED 80000 91 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 92 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 93 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 94 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 95 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 96 #define CONFIG_SYS_I2C_PINMUX_SET (0) 97 98 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 99 100 #if defined(CONFIG_CMD_KGDB) 101 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 102 #else 103 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 104 #endif 105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 106 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 108 109 #define CONFIG_SYS_LOAD_ADDR 0x00100000 110 111 #define CONFIG_SYS_MEMTEST_START 0x400 112 #define CONFIG_SYS_MEMTEST_END 0x380000 113 114 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 115 #define CONFIG_SYS_FAST_CLK 116 #ifdef CONFIG_SYS_FAST_CLK 117 # define CONFIG_SYS_PLLCR 0x1243E054 118 # define CONFIG_SYS_CLK 140000000 119 #else 120 # define CONFIG_SYS_PLLCR 0x135a4140 121 # define CONFIG_SYS_CLK 70000000 122 #endif 123 124 /* 125 * Low Level Configuration Settings 126 * (address mappings, register initial values, etc.) 127 * You should know what you are doing if you make changes here. 128 */ 129 130 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 131 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 132 133 /* 134 * Definitions for initial stack pointer and data area (in DPRAM) 135 */ 136 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 137 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 138 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 139 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 140 141 /* 142 * Start addresses for the final memory configuration 143 * (Set up by the startup code) 144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 145 */ 146 #define CONFIG_SYS_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 148 149 #ifdef CONFIG_MONITOR_IS_IN_RAM 150 # define CONFIG_SYS_MONITOR_BASE 0x20000 151 #else 152 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 153 #endif 154 155 #define CONFIG_SYS_MONITOR_LEN 0x40000 156 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 157 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 158 159 /* 160 * For booting Linux, the board info and command line data 161 * have to be in the first 8 MB of memory, since this is 162 * the maximum mapped by the Linux kernel during initialization ?? 163 */ 164 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 165 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 166 167 /* FLASH organization */ 168 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 169 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 170 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 171 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 172 173 #define FLASH_SST6401B 0x200 174 #define SST_ID_xF6401B 0x236D236D 175 176 #undef CONFIG_SYS_FLASH_CFI 177 #ifdef CONFIG_SYS_FLASH_CFI 178 /* 179 * Unable to use CFI driver, due to incompatible sector erase command by SST. 180 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 181 * 0x30 is block erase in SST 182 */ 183 # define CONFIG_FLASH_CFI_DRIVER 1 184 # define CONFIG_SYS_FLASH_SIZE 0x800000 185 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 186 # define CONFIG_FLASH_CFI_LEGACY 187 #else 188 # define CONFIG_SYS_SST_SECT 2048 189 # define CONFIG_SYS_SST_SECTSZ 0x1000 190 # define CONFIG_SYS_FLASH_WRITE_TOUT 500 191 #endif 192 193 /* Cache Configuration */ 194 #define CONFIG_SYS_CACHELINE_SIZE 16 195 196 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 197 CONFIG_SYS_INIT_RAM_SIZE - 8) 198 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 199 CONFIG_SYS_INIT_RAM_SIZE - 4) 200 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 201 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 202 CF_ADDRMASK(8) | \ 203 CF_ACR_EN | CF_ACR_SM_ALL) 204 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 205 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 206 CF_ACR_EN | CF_ACR_SM_ALL) 207 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 208 CF_CACR_DBWE) 209 210 /* Port configuration */ 211 #define CONFIG_SYS_FECI2C 0xF0 212 213 #define CONFIG_SYS_CS0_BASE 0xFF800000 214 #define CONFIG_SYS_CS0_MASK 0x007F0021 215 #define CONFIG_SYS_CS0_CTRL 0x00001D80 216 217 #define CONFIG_SYS_CS1_BASE 0xE0000000 218 #define CONFIG_SYS_CS1_MASK 0x00000001 219 #define CONFIG_SYS_CS1_CTRL 0x00003DD8 220 221 /*----------------------------------------------------------------------- 222 * Port configuration 223 */ 224 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 225 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 226 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 227 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 228 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 229 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 230 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 231 232 #endif /* _M5253DEMO_H */ 233