1 /* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5249EVB_H 15 #define _M5249EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF52x2 /* define processor family */ 22 #define CONFIG_M5249 /* define processor type */ 23 24 #define CONFIG_MCFTMR 25 26 #define CONFIG_MCFUART 27 #define CONFIG_SYS_UART_PORT (0) 28 #define CONFIG_BAUDRATE 115200 29 30 #undef CONFIG_WATCHDOG 31 32 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 33 34 /* 35 * BOOTP options 36 */ 37 #undef CONFIG_BOOTP_BOOTFILESIZE 38 #undef CONFIG_BOOTP_BOOTPATH 39 #undef CONFIG_BOOTP_GATEWAY 40 #undef CONFIG_BOOTP_HOSTNAME 41 42 /* 43 * Command line configuration. 44 */ 45 #include <config_cmd_default.h> 46 #define CONFIG_CMD_CACHE 47 #undef CONFIG_CMD_NET 48 49 #define CONFIG_SYS_PROMPT "=> " 50 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 51 52 #if defined(CONFIG_CMD_KGDB) 53 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 54 #else 55 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 56 #endif 57 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 58 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 60 61 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 62 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ 63 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 64 #define CONFIG_LOOPW 1 /* enable loopw command */ 65 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 66 67 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 68 69 #define CONFIG_SYS_MEMTEST_START 0x400 70 #define CONFIG_SYS_MEMTEST_END 0x380000 71 72 #define CONFIG_SYS_HZ 1000 73 74 /* 75 * Clock configuration: enable only one of the following options 76 */ 77 78 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 79 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 80 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 81 82 /* 83 * Low Level Configuration Settings 84 * (address mappings, register initial values, etc.) 85 * You should know what you are doing if you make changes here. 86 */ 87 88 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 89 #define CONFIG_SYS_MBAR2 0x80000000 90 91 /*----------------------------------------------------------------------- 92 * Definitions for initial stack pointer and data area (in DPRAM) 93 */ 94 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 95 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 96 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 97 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 98 99 #define CONFIG_ENV_IS_IN_FLASH 1 100 #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 101 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 102 #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 103 104 /*----------------------------------------------------------------------- 105 * Start addresses for the final memory configuration 106 * (Set up by the startup code) 107 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 108 */ 109 #define CONFIG_SYS_SDRAM_BASE 0x00000000 110 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 111 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 112 113 #if 0 /* test-only */ 114 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 115 #endif 116 117 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 118 119 #define CONFIG_SYS_MONITOR_LEN 0x20000 120 #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 121 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 122 123 /* 124 * For booting Linux, the board info and command line data 125 * have to be in the first 8 MB of memory, since this is 126 * the maximum mapped by the Linux kernel during initialization ?? 127 */ 128 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 129 130 /*----------------------------------------------------------------------- 131 * FLASH organization 132 */ 133 #define CONFIG_SYS_FLASH_CFI 134 #ifdef CONFIG_SYS_FLASH_CFI 135 136 # define CONFIG_FLASH_CFI_DRIVER 1 137 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 138 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 139 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 140 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 141 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 142 # define CONFIG_SYS_FLASH_CHECKSUM 143 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 144 #endif 145 146 /*----------------------------------------------------------------------- 147 * Cache Configuration 148 */ 149 #define CONFIG_SYS_CACHELINE_SIZE 16 150 151 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 152 CONFIG_SYS_INIT_RAM_SIZE - 8) 153 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 154 CONFIG_SYS_INIT_RAM_SIZE - 4) 155 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 156 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 157 CF_ADDRMASK(2) | \ 158 CF_ACR_EN | CF_ACR_SM_ALL) 159 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 160 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 161 CF_ACR_EN | CF_ACR_SM_ALL) 162 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 163 CF_CACR_DBWE) 164 165 /*----------------------------------------------------------------------- 166 * Memory bank definitions 167 */ 168 169 /* CS0 - AMD Flash, address 0xffc00000 */ 170 #define CONFIG_SYS_CS0_BASE 0xffe00000 171 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 172 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 173 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 174 175 /* CS1 - FPGA, address 0xe0000000 */ 176 #define CONFIG_SYS_CS1_BASE 0xe0000000 177 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 178 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 179 180 /*----------------------------------------------------------------------- 181 * Port configuration 182 */ 183 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 184 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 185 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 186 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 187 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 188 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 189 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 190 191 #endif /* M5249 */ 192