1 /* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5249EVB_H 15 #define _M5249EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCFTMR 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 30 31 /* 32 * BOOTP options 33 */ 34 #undef CONFIG_BOOTP_BOOTFILESIZE 35 #undef CONFIG_BOOTP_BOOTPATH 36 #undef CONFIG_BOOTP_GATEWAY 37 #undef CONFIG_BOOTP_HOSTNAME 38 39 /* 40 * Command line configuration. 41 */ 42 #define CONFIG_CMD_CACHE 43 44 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 45 46 #if defined(CONFIG_CMD_KGDB) 47 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 48 #else 49 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 50 #endif 51 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 52 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 53 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 54 55 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 56 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ 57 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 58 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 59 60 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 61 62 #define CONFIG_SYS_MEMTEST_START 0x400 63 #define CONFIG_SYS_MEMTEST_END 0x380000 64 65 /* 66 * Clock configuration: enable only one of the following options 67 */ 68 69 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 70 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 71 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 72 73 /* 74 * Low Level Configuration Settings 75 * (address mappings, register initial values, etc.) 76 * You should know what you are doing if you make changes here. 77 */ 78 79 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 80 #define CONFIG_SYS_MBAR2 0x80000000 81 82 /*----------------------------------------------------------------------- 83 * Definitions for initial stack pointer and data area (in DPRAM) 84 */ 85 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 86 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 87 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 88 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 89 90 #define CONFIG_ENV_IS_IN_FLASH 1 91 92 #define LDS_BOARD_TEXT \ 93 . = DEFINED(env_offset) ? env_offset : .; \ 94 common/env_embedded.o (.text); 95 96 #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 97 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 98 #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 99 100 /*----------------------------------------------------------------------- 101 * Start addresses for the final memory configuration 102 * (Set up by the startup code) 103 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 104 */ 105 #define CONFIG_SYS_SDRAM_BASE 0x00000000 106 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 107 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 108 109 #if 0 /* test-only */ 110 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 111 #endif 112 113 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 114 115 #define CONFIG_SYS_MONITOR_LEN 0x20000 116 #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 117 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 118 119 /* 120 * For booting Linux, the board info and command line data 121 * have to be in the first 8 MB of memory, since this is 122 * the maximum mapped by the Linux kernel during initialization ?? 123 */ 124 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 125 126 /*----------------------------------------------------------------------- 127 * FLASH organization 128 */ 129 #define CONFIG_SYS_FLASH_CFI 130 #ifdef CONFIG_SYS_FLASH_CFI 131 132 # define CONFIG_FLASH_CFI_DRIVER 1 133 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 134 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 135 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 136 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 137 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 138 # define CONFIG_SYS_FLASH_CHECKSUM 139 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 140 #endif 141 142 /*----------------------------------------------------------------------- 143 * Cache Configuration 144 */ 145 #define CONFIG_SYS_CACHELINE_SIZE 16 146 147 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 148 CONFIG_SYS_INIT_RAM_SIZE - 8) 149 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 150 CONFIG_SYS_INIT_RAM_SIZE - 4) 151 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 152 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 153 CF_ADDRMASK(2) | \ 154 CF_ACR_EN | CF_ACR_SM_ALL) 155 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 156 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 157 CF_ACR_EN | CF_ACR_SM_ALL) 158 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 159 CF_CACR_DBWE) 160 161 /*----------------------------------------------------------------------- 162 * Memory bank definitions 163 */ 164 165 /* CS0 - AMD Flash, address 0xffc00000 */ 166 #define CONFIG_SYS_CS0_BASE 0xffe00000 167 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 168 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 169 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 170 171 /* CS1 - FPGA, address 0xe0000000 */ 172 #define CONFIG_SYS_CS1_BASE 0xe0000000 173 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 174 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 175 176 /*----------------------------------------------------------------------- 177 * Port configuration 178 */ 179 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 180 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 181 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 182 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 183 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 184 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 185 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 186 187 #endif /* M5249 */ 188