xref: /openbmc/u-boot/include/configs/M5249EVB.h (revision 6d0f6bcf)
1 /*
2  * Configuation settings for the esd TASREG board.
3  *
4  * (C) Copyright 2004
5  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 /*
27  * board/config.h - configuration options, board specific
28  */
29 
30 #ifndef _M5249EVB_H
31 #define _M5249EVB_H
32 
33 /*
34  * High Level Configuration Options
35  * (easy to change)
36  */
37 #define CONFIG_MCF52x2			/* define processor family */
38 #define CONFIG_M5249			/* define processor type */
39 
40 #define CONFIG_MCFTMR
41 
42 #define CONFIG_MCFUART
43 #define CONFIG_SYS_UART_PORT		(0)
44 #define CONFIG_BAUDRATE		115200
45 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
46 
47 #undef  CONFIG_WATCHDOG
48 
49 #undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */
50 
51 /*
52  * BOOTP options
53  */
54 #undef CONFIG_BOOTP_BOOTFILESIZE
55 #undef CONFIG_BOOTP_BOOTPATH
56 #undef CONFIG_BOOTP_GATEWAY
57 #undef CONFIG_BOOTP_HOSTNAME
58 
59 /*
60  * Command line configuration.
61  */
62 #include <config_cmd_default.h>
63 #undef CONFIG_CMD_NET
64 
65 #define CONFIG_SYS_PROMPT		"=> "
66 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
67 
68 #if defined(CONFIG_CMD_KGDB)
69 #define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
70 #else
71 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
72 #endif
73 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
74 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
75 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
76 
77 #define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
78 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
79 #define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
80 #define CONFIG_LOOPW		1	/* enable loopw command	*/
81 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
82 
83 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
84 
85 #define CONFIG_SYS_MEMTEST_START	0x400
86 #define CONFIG_SYS_MEMTEST_END		0x380000
87 
88 #define CONFIG_SYS_HZ			1000
89 
90 /*
91  * Clock configuration: enable only one of the following options
92  */
93 
94 #undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
95 #define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
96 #define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
97 
98 /*
99  * Low Level Configuration Settings
100  * (address mappings, register initial values, etc.)
101  * You should know what you are doing if you make changes here.
102  */
103 
104 #define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
105 #define	CONFIG_SYS_MBAR2		0x80000000
106 
107 /*-----------------------------------------------------------------------
108  * Definitions for initial stack pointer and data area (in DPRAM)
109  */
110 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
111 #define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
112 #define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
113 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
114 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
115 
116 #define CONFIG_ENV_IS_IN_FLASH	1
117 #define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
118 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
119 #define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
120 
121 /*-----------------------------------------------------------------------
122  * Start addresses for the final memory configuration
123  * (Set up by the startup code)
124  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
125  */
126 #define CONFIG_SYS_SDRAM_BASE		0x00000000
127 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
128 #define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
129 
130 #if 0 /* test-only */
131 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
132 #endif
133 
134 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
135 
136 #define CONFIG_SYS_MONITOR_LEN		0x20000
137 #define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
138 #define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
139 
140 /*
141  * For booting Linux, the board info and command line data
142  * have to be in the first 8 MB of memory, since this is
143  * the maximum mapped by the Linux kernel during initialization ??
144  */
145 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
146 
147 /*-----------------------------------------------------------------------
148  * FLASH organization
149  */
150 #define CONFIG_SYS_FLASH_CFI
151 #ifdef CONFIG_SYS_FLASH_CFI
152 
153 #	define CONFIG_FLASH_CFI_DRIVER	1
154 #	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
155 #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
156 #	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
157 #	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
158 #	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
159 #	define CONFIG_SYS_FLASH_CHECKSUM
160 #	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
161 #endif
162 
163 /*-----------------------------------------------------------------------
164  * Cache Configuration
165  */
166 #define CONFIG_SYS_CACHELINE_SIZE	16
167 
168 /*-----------------------------------------------------------------------
169  * Memory bank definitions
170  */
171 
172 /* CS0 - AMD Flash, address 0xffc00000 */
173 #define	CONFIG_SYS_CSAR0		0xffe0
174 #define	CONFIG_SYS_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
175 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
176 #define	CONFIG_SYS_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
177 
178 /* CS1 - FPGA, address 0xe0000000 */
179 #define	CONFIG_SYS_CSAR1		0xe000
180 #define	CONFIG_SYS_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
181 #define	CONFIG_SYS_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
182 
183 /*-----------------------------------------------------------------------
184  * Port configuration
185  */
186 #define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
187 #define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
188 #define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
189 #define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
190 #define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
191 #define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
192 #define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
193 
194 #endif	/* M5249 */
195