1 /* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5249EVB_H 15 #define _M5249EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCFTMR 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 29 30 /* 31 * BOOTP options 32 */ 33 #undef CONFIG_BOOTP_BOOTFILESIZE 34 #undef CONFIG_BOOTP_BOOTPATH 35 #undef CONFIG_BOOTP_GATEWAY 36 #undef CONFIG_BOOTP_HOSTNAME 37 38 /* 39 * Command line configuration. 40 */ 41 42 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 43 44 #if defined(CONFIG_CMD_KGDB) 45 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 46 #else 47 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 48 #endif 49 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 50 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 51 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 52 53 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 54 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 55 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 56 57 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 58 59 #define CONFIG_SYS_MEMTEST_START 0x400 60 #define CONFIG_SYS_MEMTEST_END 0x380000 61 62 /* 63 * Clock configuration: enable only one of the following options 64 */ 65 66 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 67 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 68 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 69 70 /* 71 * Low Level Configuration Settings 72 * (address mappings, register initial values, etc.) 73 * You should know what you are doing if you make changes here. 74 */ 75 76 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 77 #define CONFIG_SYS_MBAR2 0x80000000 78 79 /*----------------------------------------------------------------------- 80 * Definitions for initial stack pointer and data area (in DPRAM) 81 */ 82 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 83 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 84 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 85 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 86 87 #define LDS_BOARD_TEXT \ 88 . = DEFINED(env_offset) ? env_offset : .; \ 89 common/env_embedded.o (.text); 90 91 #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 92 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 93 #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 94 95 /*----------------------------------------------------------------------- 96 * Start addresses for the final memory configuration 97 * (Set up by the startup code) 98 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 99 */ 100 #define CONFIG_SYS_SDRAM_BASE 0x00000000 101 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 102 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 103 104 #if 0 /* test-only */ 105 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 106 #endif 107 108 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 109 110 #define CONFIG_SYS_MONITOR_LEN 0x20000 111 #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 112 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 113 114 /* 115 * For booting Linux, the board info and command line data 116 * have to be in the first 8 MB of memory, since this is 117 * the maximum mapped by the Linux kernel during initialization ?? 118 */ 119 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 120 121 /*----------------------------------------------------------------------- 122 * FLASH organization 123 */ 124 #define CONFIG_SYS_FLASH_CFI 125 #ifdef CONFIG_SYS_FLASH_CFI 126 127 # define CONFIG_FLASH_CFI_DRIVER 1 128 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 129 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 130 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 131 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 132 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 133 # define CONFIG_SYS_FLASH_CHECKSUM 134 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 135 #endif 136 137 /*----------------------------------------------------------------------- 138 * Cache Configuration 139 */ 140 #define CONFIG_SYS_CACHELINE_SIZE 16 141 142 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 143 CONFIG_SYS_INIT_RAM_SIZE - 8) 144 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 145 CONFIG_SYS_INIT_RAM_SIZE - 4) 146 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 147 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 148 CF_ADDRMASK(2) | \ 149 CF_ACR_EN | CF_ACR_SM_ALL) 150 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 151 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 152 CF_ACR_EN | CF_ACR_SM_ALL) 153 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 154 CF_CACR_DBWE) 155 156 /*----------------------------------------------------------------------- 157 * Memory bank definitions 158 */ 159 160 /* CS0 - AMD Flash, address 0xffc00000 */ 161 #define CONFIG_SYS_CS0_BASE 0xffe00000 162 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 163 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 164 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 165 166 /* CS1 - FPGA, address 0xe0000000 */ 167 #define CONFIG_SYS_CS1_BASE 0xe0000000 168 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 169 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 170 171 /*----------------------------------------------------------------------- 172 * Port configuration 173 */ 174 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 175 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 176 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 177 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 178 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 179 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 180 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 181 182 #endif /* M5249 */ 183