1 /* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5249EVB_H 15 #define _M5249EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCFTMR 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 29 30 /* 31 * BOOTP options 32 */ 33 #undef CONFIG_BOOTP_BOOTFILESIZE 34 #undef CONFIG_BOOTP_BOOTPATH 35 #undef CONFIG_BOOTP_GATEWAY 36 #undef CONFIG_BOOTP_HOSTNAME 37 38 /* 39 * Command line configuration. 40 */ 41 42 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 43 44 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 45 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 46 47 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 48 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 49 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 50 51 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 52 53 #define CONFIG_SYS_MEMTEST_START 0x400 54 #define CONFIG_SYS_MEMTEST_END 0x380000 55 56 /* 57 * Clock configuration: enable only one of the following options 58 */ 59 60 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 61 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 62 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 63 64 /* 65 * Low Level Configuration Settings 66 * (address mappings, register initial values, etc.) 67 * You should know what you are doing if you make changes here. 68 */ 69 70 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 71 #define CONFIG_SYS_MBAR2 0x80000000 72 73 /*----------------------------------------------------------------------- 74 * Definitions for initial stack pointer and data area (in DPRAM) 75 */ 76 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 77 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 78 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 79 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 80 81 #define LDS_BOARD_TEXT \ 82 . = DEFINED(env_offset) ? env_offset : .; \ 83 env/embedded.o(.text); 84 85 #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 86 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 87 #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 88 89 /*----------------------------------------------------------------------- 90 * Start addresses for the final memory configuration 91 * (Set up by the startup code) 92 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 93 */ 94 #define CONFIG_SYS_SDRAM_BASE 0x00000000 95 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 96 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 97 98 #if 0 /* test-only */ 99 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 100 #endif 101 102 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 103 104 #define CONFIG_SYS_MONITOR_LEN 0x20000 105 #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 106 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 107 108 /* 109 * For booting Linux, the board info and command line data 110 * have to be in the first 8 MB of memory, since this is 111 * the maximum mapped by the Linux kernel during initialization ?? 112 */ 113 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 114 115 /*----------------------------------------------------------------------- 116 * FLASH organization 117 */ 118 #define CONFIG_SYS_FLASH_CFI 119 #ifdef CONFIG_SYS_FLASH_CFI 120 121 # define CONFIG_FLASH_CFI_DRIVER 1 122 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 123 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 124 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 125 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 126 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 127 # define CONFIG_SYS_FLASH_CHECKSUM 128 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 129 #endif 130 131 /*----------------------------------------------------------------------- 132 * Cache Configuration 133 */ 134 #define CONFIG_SYS_CACHELINE_SIZE 16 135 136 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 137 CONFIG_SYS_INIT_RAM_SIZE - 8) 138 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 139 CONFIG_SYS_INIT_RAM_SIZE - 4) 140 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 141 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 142 CF_ADDRMASK(2) | \ 143 CF_ACR_EN | CF_ACR_SM_ALL) 144 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 145 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 146 CF_ACR_EN | CF_ACR_SM_ALL) 147 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 148 CF_CACR_DBWE) 149 150 /*----------------------------------------------------------------------- 151 * Memory bank definitions 152 */ 153 154 /* CS0 - AMD Flash, address 0xffc00000 */ 155 #define CONFIG_SYS_CS0_BASE 0xffe00000 156 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 157 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 158 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 159 160 /* CS1 - FPGA, address 0xe0000000 */ 161 #define CONFIG_SYS_CS1_BASE 0xe0000000 162 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 163 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 164 165 /*----------------------------------------------------------------------- 166 * Port configuration 167 */ 168 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 169 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 170 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 171 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 172 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 173 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 174 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 175 176 #endif /* M5249 */ 177