1 /* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5249EVB_H 31 #define _M5249EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF52x2 /* define processor family */ 38 #define CONFIG_M5249 /* define processor type */ 39 40 #define CONFIG_MCFTMR 41 42 #define CONFIG_MCFUART 43 #define CONFIG_SYS_UART_PORT (0) 44 #define CONFIG_BAUDRATE 115200 45 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 46 47 #undef CONFIG_WATCHDOG 48 49 #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 50 51 /* 52 * BOOTP options 53 */ 54 #undef CONFIG_BOOTP_BOOTFILESIZE 55 #undef CONFIG_BOOTP_BOOTPATH 56 #undef CONFIG_BOOTP_GATEWAY 57 #undef CONFIG_BOOTP_HOSTNAME 58 59 /* 60 * Command line configuration. 61 */ 62 #include <config_cmd_default.h> 63 #define CONFIG_CMD_CACHE 64 #undef CONFIG_CMD_NET 65 66 #define CONFIG_SYS_PROMPT "=> " 67 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 68 69 #if defined(CONFIG_CMD_KGDB) 70 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 71 #else 72 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 73 #endif 74 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 75 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 76 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 77 78 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 79 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ 80 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 81 #define CONFIG_LOOPW 1 /* enable loopw command */ 82 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 83 84 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 85 86 #define CONFIG_SYS_MEMTEST_START 0x400 87 #define CONFIG_SYS_MEMTEST_END 0x380000 88 89 #define CONFIG_SYS_HZ 1000 90 91 /* 92 * Clock configuration: enable only one of the following options 93 */ 94 95 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 96 #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 97 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 98 99 /* 100 * Low Level Configuration Settings 101 * (address mappings, register initial values, etc.) 102 * You should know what you are doing if you make changes here. 103 */ 104 105 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 106 #define CONFIG_SYS_MBAR2 0x80000000 107 108 /*----------------------------------------------------------------------- 109 * Definitions for initial stack pointer and data area (in DPRAM) 110 */ 111 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 112 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ 113 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 114 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 115 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 116 117 #define CONFIG_ENV_IS_IN_FLASH 1 118 #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 119 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 120 #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 121 122 /*----------------------------------------------------------------------- 123 * Start addresses for the final memory configuration 124 * (Set up by the startup code) 125 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 126 */ 127 #define CONFIG_SYS_SDRAM_BASE 0x00000000 128 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 129 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 130 131 #if 0 /* test-only */ 132 #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 133 #endif 134 135 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 136 137 #define CONFIG_SYS_MONITOR_LEN 0x20000 138 #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 139 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 140 141 /* 142 * For booting Linux, the board info and command line data 143 * have to be in the first 8 MB of memory, since this is 144 * the maximum mapped by the Linux kernel during initialization ?? 145 */ 146 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 147 148 /*----------------------------------------------------------------------- 149 * FLASH organization 150 */ 151 #define CONFIG_SYS_FLASH_CFI 152 #ifdef CONFIG_SYS_FLASH_CFI 153 154 # define CONFIG_FLASH_CFI_DRIVER 1 155 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 156 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 157 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 158 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 159 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 160 # define CONFIG_SYS_FLASH_CHECKSUM 161 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 162 #endif 163 164 /*----------------------------------------------------------------------- 165 * Cache Configuration 166 */ 167 #define CONFIG_SYS_CACHELINE_SIZE 16 168 169 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 170 CONFIG_SYS_INIT_RAM_END - 8) 171 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 172 CONFIG_SYS_INIT_RAM_END - 4) 173 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 174 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 175 CF_ADDRMASK(2) | \ 176 CF_ACR_EN | CF_ACR_SM_ALL) 177 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 178 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 179 CF_ACR_EN | CF_ACR_SM_ALL) 180 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 181 CF_CACR_DBWE) 182 183 /*----------------------------------------------------------------------- 184 * Memory bank definitions 185 */ 186 187 /* CS0 - AMD Flash, address 0xffc00000 */ 188 #define CONFIG_SYS_CS0_BASE 0xffe00000 189 #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 190 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 191 #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 192 193 /* CS1 - FPGA, address 0xe0000000 */ 194 #define CONFIG_SYS_CS1_BASE 0xe0000000 195 #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 196 #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 197 198 /*----------------------------------------------------------------------- 199 * Port configuration 200 */ 201 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 202 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 203 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 204 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 205 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 206 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 207 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 208 209 #endif /* M5249 */ 210