1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5235EVB_H 31 #define _M5235EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF523x /* define processor family */ 38 #define CONFIG_M5235 /* define processor type */ 39 40 #define CONFIG_MCFUART 41 #define CONFIG_SYS_UART_PORT (0) 42 #define CONFIG_BAUDRATE 115200 43 44 #undef CONFIG_WATCHDOG 45 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 46 47 /* 48 * BOOTP options 49 */ 50 #define CONFIG_BOOTP_BOOTFILESIZE 51 #define CONFIG_BOOTP_BOOTPATH 52 #define CONFIG_BOOTP_GATEWAY 53 #define CONFIG_BOOTP_HOSTNAME 54 55 /* Command line configuration */ 56 #include <config_cmd_default.h> 57 58 #define CONFIG_CMD_BOOTD 59 #define CONFIG_CMD_CACHE 60 #define CONFIG_CMD_DHCP 61 #define CONFIG_CMD_ELF 62 #define CONFIG_CMD_FLASH 63 #define CONFIG_CMD_I2C 64 #define CONFIG_CMD_MEMORY 65 #define CONFIG_CMD_MISC 66 #define CONFIG_CMD_MII 67 #define CONFIG_CMD_NET 68 #define CONFIG_CMD_PCI 69 #define CONFIG_CMD_PING 70 #define CONFIG_CMD_REGINFO 71 72 #undef CONFIG_CMD_LOADB 73 #undef CONFIG_CMD_LOADS 74 75 #define CONFIG_MCFFEC 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_MII 1 78 # define CONFIG_MII_INIT 1 79 # define CONFIG_SYS_DISCOVER_PHY 80 # define CONFIG_SYS_RX_ETH_BUFFER 8 81 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 82 83 # define CONFIG_SYS_FEC0_PINMUX 0 84 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 85 # define MCFFEC_TOUT_LOOP 50000 86 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 87 # ifndef CONFIG_SYS_DISCOVER_PHY 88 # define FECDUPLEX FULL 89 # define FECSPEED _100BASET 90 # else 91 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 92 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 93 # endif 94 # endif /* CONFIG_SYS_DISCOVER_PHY */ 95 #endif 96 97 /* Timer */ 98 #define CONFIG_MCFTMR 99 #undef CONFIG_MCFPIT 100 101 /* I2C */ 102 #define CONFIG_FSL_I2C 103 #define CONFIG_HARD_I2C /* I2C with hw support */ 104 #define CONFIG_SYS_I2C_SPEED 80000 105 #define CONFIG_SYS_I2C_SLAVE 0x7F 106 #define CONFIG_SYS_I2C_OFFSET 0x00000300 107 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 108 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 109 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 110 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 111 112 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 113 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 114 #define CONFIG_BOOTFILE "u-boot.bin" 115 #ifdef CONFIG_MCFFEC 116 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 117 # define CONFIG_IPADDR 192.162.1.2 118 # define CONFIG_NETMASK 255.255.255.0 119 # define CONFIG_SERVERIP 192.162.1.1 120 # define CONFIG_GATEWAYIP 192.162.1.1 121 # define CONFIG_OVERWRITE_ETHADDR_ONCE 122 #endif /* FEC_ENET */ 123 124 #define CONFIG_HOSTNAME M5235EVB 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "netdev=eth0\0" \ 127 "loadaddr=10000\0" \ 128 "u-boot=u-boot.bin\0" \ 129 "load=tftp ${loadaddr) ${u-boot}\0" \ 130 "upd=run load; run prog\0" \ 131 "prog=prot off ffe00000 ffe3ffff;" \ 132 "era ffe00000 ffe3ffff;" \ 133 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 134 "save\0" \ 135 "" 136 137 #define CONFIG_PRAM 512 /* 512 KB */ 138 #define CONFIG_SYS_PROMPT "-> " 139 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 140 141 #if defined(CONFIG_KGDB) 142 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 143 #else 144 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 145 #endif 146 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 148 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 149 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 150 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 151 152 #define CONFIG_SYS_HZ 1000 153 #define CONFIG_SYS_CLK 75000000 154 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 155 156 #define CONFIG_SYS_MBAR 0x40000000 157 158 /* 159 * Low Level Configuration Settings 160 * (address mappings, register initial values, etc.) 161 * You should know what you are doing if you make changes here. 162 */ 163 /*----------------------------------------------------------------------- 164 * Definitions for initial stack pointer and data area (in DPRAM) 165 */ 166 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 167 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 168 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 169 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 170 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 171 172 /*----------------------------------------------------------------------- 173 * Start addresses for the final memory configuration 174 * (Set up by the startup code) 175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 176 */ 177 #define CONFIG_SYS_SDRAM_BASE 0x00000000 178 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 179 180 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 181 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 182 183 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 185 186 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 187 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 188 189 /* 190 * For booting Linux, the board info and command line data 191 * have to be in the first 8 MB of memory, since this is 192 * the maximum mapped by the Linux kernel during initialization ?? 193 */ 194 /* Initial Memory map for Linux */ 195 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 196 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 197 198 /*----------------------------------------------------------------------- 199 * FLASH organization 200 */ 201 #define CONFIG_SYS_FLASH_CFI 202 #ifdef CONFIG_SYS_FLASH_CFI 203 # define CONFIG_FLASH_CFI_DRIVER 1 204 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 205 #ifdef NORFLASH_PS32BIT 206 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 207 #else 208 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 209 #endif 210 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 211 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 212 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 213 #endif 214 215 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 216 217 /* Configuration for environment 218 * Environment is embedded in u-boot in the second sector of the flash 219 */ 220 #define CONFIG_ENV_IS_IN_FLASH 1 221 #ifdef NORFLASH_PS32BIT 222 # define CONFIG_ENV_OFFSET (0x8000) 223 # define CONFIG_ENV_SIZE 0x4000 224 # define CONFIG_ENV_SECT_SIZE 0x4000 225 #else 226 # define CONFIG_ENV_OFFSET (0x4000) 227 # define CONFIG_ENV_SIZE 0x2000 228 # define CONFIG_ENV_SECT_SIZE 0x2000 229 #endif 230 231 /*----------------------------------------------------------------------- 232 * Cache Configuration 233 */ 234 #define CONFIG_SYS_CACHELINE_SIZE 16 235 236 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 237 CONFIG_SYS_INIT_RAM_SIZE - 8) 238 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 239 CONFIG_SYS_INIT_RAM_SIZE - 4) 240 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 241 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 242 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 243 CF_ACR_EN | CF_ACR_SM_ALL) 244 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 245 CF_CACR_CEIB | CF_CACR_DCM | \ 246 CF_CACR_EUSP) 247 248 /*----------------------------------------------------------------------- 249 * Chipselect bank definitions 250 */ 251 /* 252 * CS0 - NOR Flash 1, 2, 4, or 8MB 253 * CS1 - Available 254 * CS2 - Available 255 * CS3 - Available 256 * CS4 - Available 257 * CS5 - Available 258 * CS6 - Available 259 * CS7 - Available 260 */ 261 #ifdef NORFLASH_PS32BIT 262 # define CONFIG_SYS_CS0_BASE 0xFFC00000 263 # define CONFIG_SYS_CS0_MASK 0x003f0001 264 # define CONFIG_SYS_CS0_CTRL 0x00001D00 265 #else 266 # define CONFIG_SYS_CS0_BASE 0xFFE00000 267 # define CONFIG_SYS_CS0_MASK 0x001f0001 268 # define CONFIG_SYS_CS0_CTRL 0x00001D80 269 #endif 270 271 #endif /* _M5329EVB_H */ 272