1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5329 FireEngine board. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5235EVB_H 14 #define _M5235EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27 /* 28 * BOOTP options 29 */ 30 #define CONFIG_BOOTP_BOOTFILESIZE 31 32 #define CONFIG_MCFFEC 33 #ifdef CONFIG_MCFFEC 34 # define CONFIG_MII 1 35 # define CONFIG_MII_INIT 1 36 # define CONFIG_SYS_DISCOVER_PHY 37 # define CONFIG_SYS_RX_ETH_BUFFER 8 38 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 40 # define CONFIG_SYS_FEC0_PINMUX 0 41 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 42 # define MCFFEC_TOUT_LOOP 50000 43 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 44 # ifndef CONFIG_SYS_DISCOVER_PHY 45 # define FECDUPLEX FULL 46 # define FECSPEED _100BASET 47 # else 48 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50 # endif 51 # endif /* CONFIG_SYS_DISCOVER_PHY */ 52 #endif 53 54 /* Timer */ 55 #define CONFIG_MCFTMR 56 #undef CONFIG_MCFPIT 57 58 /* I2C */ 59 #define CONFIG_SYS_I2C 60 #define CONFIG_SYS_i2C_FSL 61 #define CONFIG_SYS_FSL_I2C_SPEED 80000 62 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 63 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 64 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 65 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 66 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 67 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 68 69 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 70 #define CONFIG_BOOTFILE "u-boot.bin" 71 #ifdef CONFIG_MCFFEC 72 # define CONFIG_IPADDR 192.162.1.2 73 # define CONFIG_NETMASK 255.255.255.0 74 # define CONFIG_SERVERIP 192.162.1.1 75 # define CONFIG_GATEWAYIP 192.162.1.1 76 #endif /* FEC_ENET */ 77 78 #define CONFIG_HOSTNAME "M5235EVB" 79 #define CONFIG_EXTRA_ENV_SETTINGS \ 80 "netdev=eth0\0" \ 81 "loadaddr=10000\0" \ 82 "u-boot=u-boot.bin\0" \ 83 "load=tftp ${loadaddr) ${u-boot}\0" \ 84 "upd=run load; run prog\0" \ 85 "prog=prot off ffe00000 ffe3ffff;" \ 86 "era ffe00000 ffe3ffff;" \ 87 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 88 "save\0" \ 89 "" 90 91 #define CONFIG_PRAM 512 /* 512 KB */ 92 93 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 94 95 #define CONFIG_SYS_CLK 75000000 96 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 97 98 #define CONFIG_SYS_MBAR 0x40000000 99 100 /* 101 * Low Level Configuration Settings 102 * (address mappings, register initial values, etc.) 103 * You should know what you are doing if you make changes here. 104 */ 105 /*----------------------------------------------------------------------- 106 * Definitions for initial stack pointer and data area (in DPRAM) 107 */ 108 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 109 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 110 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 111 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 112 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 113 114 /*----------------------------------------------------------------------- 115 * Start addresses for the final memory configuration 116 * (Set up by the startup code) 117 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 118 */ 119 #define CONFIG_SYS_SDRAM_BASE 0x00000000 120 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 121 122 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 123 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 124 125 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 126 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 127 128 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 129 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 130 131 /* 132 * For booting Linux, the board info and command line data 133 * have to be in the first 8 MB of memory, since this is 134 * the maximum mapped by the Linux kernel during initialization ?? 135 */ 136 /* Initial Memory map for Linux */ 137 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 138 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 139 140 /*----------------------------------------------------------------------- 141 * FLASH organization 142 */ 143 #define CONFIG_SYS_FLASH_CFI 144 #ifdef CONFIG_SYS_FLASH_CFI 145 # define CONFIG_FLASH_CFI_DRIVER 1 146 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 147 #ifdef NORFLASH_PS32BIT 148 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 149 #else 150 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 151 #endif 152 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 153 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 154 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 155 #endif 156 157 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 158 159 /* Configuration for environment 160 * Environment is embedded in u-boot in the second sector of the flash 161 */ 162 163 #define LDS_BOARD_TEXT \ 164 . = DEFINED(env_offset) ? env_offset : .; \ 165 env/embedded.o(.text); 166 167 #ifdef NORFLASH_PS32BIT 168 # define CONFIG_ENV_OFFSET (0x8000) 169 # define CONFIG_ENV_SIZE 0x4000 170 # define CONFIG_ENV_SECT_SIZE 0x4000 171 #else 172 # define CONFIG_ENV_OFFSET (0x4000) 173 # define CONFIG_ENV_SIZE 0x2000 174 # define CONFIG_ENV_SECT_SIZE 0x2000 175 #endif 176 177 /*----------------------------------------------------------------------- 178 * Cache Configuration 179 */ 180 #define CONFIG_SYS_CACHELINE_SIZE 16 181 182 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 183 CONFIG_SYS_INIT_RAM_SIZE - 8) 184 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 185 CONFIG_SYS_INIT_RAM_SIZE - 4) 186 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 187 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 188 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 189 CF_ACR_EN | CF_ACR_SM_ALL) 190 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 191 CF_CACR_CEIB | CF_CACR_DCM | \ 192 CF_CACR_EUSP) 193 194 /*----------------------------------------------------------------------- 195 * Chipselect bank definitions 196 */ 197 /* 198 * CS0 - NOR Flash 1, 2, 4, or 8MB 199 * CS1 - Available 200 * CS2 - Available 201 * CS3 - Available 202 * CS4 - Available 203 * CS5 - Available 204 * CS6 - Available 205 * CS7 - Available 206 */ 207 #ifdef NORFLASH_PS32BIT 208 # define CONFIG_SYS_CS0_BASE 0xFFC00000 209 # define CONFIG_SYS_CS0_MASK 0x003f0001 210 # define CONFIG_SYS_CS0_CTRL 0x00001D00 211 #else 212 # define CONFIG_SYS_CS0_BASE 0xFFE00000 213 # define CONFIG_SYS_CS0_MASK 0x001f0001 214 # define CONFIG_SYS_CS0_CTRL 0x00001D80 215 #endif 216 217 #endif /* _M5329EVB_H */ 218