1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* 30 * BOOTP options 31 */ 32 #define CONFIG_BOOTP_BOOTFILESIZE 33 #define CONFIG_BOOTP_BOOTPATH 34 #define CONFIG_BOOTP_GATEWAY 35 #define CONFIG_BOOTP_HOSTNAME 36 37 /* Command line configuration */ 38 #include <config_cmd_default.h> 39 40 #define CONFIG_CMD_BOOTD 41 #define CONFIG_CMD_CACHE 42 #define CONFIG_CMD_DHCP 43 #define CONFIG_CMD_ELF 44 #define CONFIG_CMD_FLASH 45 #define CONFIG_CMD_I2C 46 #define CONFIG_CMD_MEMORY 47 #define CONFIG_CMD_MISC 48 #define CONFIG_CMD_MII 49 #define CONFIG_CMD_NET 50 #define CONFIG_CMD_PCI 51 #define CONFIG_CMD_PING 52 #define CONFIG_CMD_REGINFO 53 54 #undef CONFIG_CMD_LOADB 55 #undef CONFIG_CMD_LOADS 56 57 #define CONFIG_MCFFEC 58 #ifdef CONFIG_MCFFEC 59 # define CONFIG_MII 1 60 # define CONFIG_MII_INIT 1 61 # define CONFIG_SYS_DISCOVER_PHY 62 # define CONFIG_SYS_RX_ETH_BUFFER 8 63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 65 # define CONFIG_SYS_FEC0_PINMUX 0 66 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 67 # define MCFFEC_TOUT_LOOP 50000 68 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 69 # ifndef CONFIG_SYS_DISCOVER_PHY 70 # define FECDUPLEX FULL 71 # define FECSPEED _100BASET 72 # else 73 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # endif 76 # endif /* CONFIG_SYS_DISCOVER_PHY */ 77 #endif 78 79 /* Timer */ 80 #define CONFIG_MCFTMR 81 #undef CONFIG_MCFPIT 82 83 /* I2C */ 84 #define CONFIG_SYS_I2C 85 #define CONFIG_SYS_i2C_FSL 86 #define CONFIG_SYS_FSL_I2C_SPEED 80000 87 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 88 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 89 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 90 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 91 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 92 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 93 94 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 95 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 96 #define CONFIG_BOOTFILE "u-boot.bin" 97 #ifdef CONFIG_MCFFEC 98 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 99 # define CONFIG_IPADDR 192.162.1.2 100 # define CONFIG_NETMASK 255.255.255.0 101 # define CONFIG_SERVERIP 192.162.1.1 102 # define CONFIG_GATEWAYIP 192.162.1.1 103 # define CONFIG_OVERWRITE_ETHADDR_ONCE 104 #endif /* FEC_ENET */ 105 106 #define CONFIG_HOSTNAME M5235EVB 107 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 "netdev=eth0\0" \ 109 "loadaddr=10000\0" \ 110 "u-boot=u-boot.bin\0" \ 111 "load=tftp ${loadaddr) ${u-boot}\0" \ 112 "upd=run load; run prog\0" \ 113 "prog=prot off ffe00000 ffe3ffff;" \ 114 "era ffe00000 ffe3ffff;" \ 115 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 116 "save\0" \ 117 "" 118 119 #define CONFIG_PRAM 512 /* 512 KB */ 120 #define CONFIG_SYS_PROMPT "-> " 121 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 122 123 #if defined(CONFIG_KGDB) 124 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 125 #else 126 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 127 #endif 128 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 133 134 #define CONFIG_SYS_CLK 75000000 135 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 136 137 #define CONFIG_SYS_MBAR 0x40000000 138 139 /* 140 * Low Level Configuration Settings 141 * (address mappings, register initial values, etc.) 142 * You should know what you are doing if you make changes here. 143 */ 144 /*----------------------------------------------------------------------- 145 * Definitions for initial stack pointer and data area (in DPRAM) 146 */ 147 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 148 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 149 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 150 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 151 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 152 153 /*----------------------------------------------------------------------- 154 * Start addresses for the final memory configuration 155 * (Set up by the startup code) 156 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 157 */ 158 #define CONFIG_SYS_SDRAM_BASE 0x00000000 159 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 160 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 162 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 163 164 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 165 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 166 167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 168 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 169 170 /* 171 * For booting Linux, the board info and command line data 172 * have to be in the first 8 MB of memory, since this is 173 * the maximum mapped by the Linux kernel during initialization ?? 174 */ 175 /* Initial Memory map for Linux */ 176 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 177 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 178 179 /*----------------------------------------------------------------------- 180 * FLASH organization 181 */ 182 #define CONFIG_SYS_FLASH_CFI 183 #ifdef CONFIG_SYS_FLASH_CFI 184 # define CONFIG_FLASH_CFI_DRIVER 1 185 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 186 #ifdef NORFLASH_PS32BIT 187 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 188 #else 189 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 190 #endif 191 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 192 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 193 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 194 #endif 195 196 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 197 198 /* Configuration for environment 199 * Environment is embedded in u-boot in the second sector of the flash 200 */ 201 #define CONFIG_ENV_IS_IN_FLASH 1 202 203 #define LDS_BOARD_TEXT \ 204 . = DEFINED(env_offset) ? env_offset : .; \ 205 common/env_embedded.o (.text); 206 207 #ifdef NORFLASH_PS32BIT 208 # define CONFIG_ENV_OFFSET (0x8000) 209 # define CONFIG_ENV_SIZE 0x4000 210 # define CONFIG_ENV_SECT_SIZE 0x4000 211 #else 212 # define CONFIG_ENV_OFFSET (0x4000) 213 # define CONFIG_ENV_SIZE 0x2000 214 # define CONFIG_ENV_SECT_SIZE 0x2000 215 #endif 216 217 /*----------------------------------------------------------------------- 218 * Cache Configuration 219 */ 220 #define CONFIG_SYS_CACHELINE_SIZE 16 221 222 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 223 CONFIG_SYS_INIT_RAM_SIZE - 8) 224 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 225 CONFIG_SYS_INIT_RAM_SIZE - 4) 226 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 227 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 228 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 229 CF_ACR_EN | CF_ACR_SM_ALL) 230 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 231 CF_CACR_CEIB | CF_CACR_DCM | \ 232 CF_CACR_EUSP) 233 234 /*----------------------------------------------------------------------- 235 * Chipselect bank definitions 236 */ 237 /* 238 * CS0 - NOR Flash 1, 2, 4, or 8MB 239 * CS1 - Available 240 * CS2 - Available 241 * CS3 - Available 242 * CS4 - Available 243 * CS5 - Available 244 * CS6 - Available 245 * CS7 - Available 246 */ 247 #ifdef NORFLASH_PS32BIT 248 # define CONFIG_SYS_CS0_BASE 0xFFC00000 249 # define CONFIG_SYS_CS0_MASK 0x003f0001 250 # define CONFIG_SYS_CS0_CTRL 0x00001D00 251 #else 252 # define CONFIG_SYS_CS0_BASE 0xFFE00000 253 # define CONFIG_SYS_CS0_MASK 0x001f0001 254 # define CONFIG_SYS_CS0_CTRL 0x00001D80 255 #endif 256 257 #endif /* _M5329EVB_H */ 258