1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5235EVB_H 31 #define _M5235EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF523x /* define processor family */ 38 #define CONFIG_M5235 /* define processor type */ 39 40 #define CONFIG_MCFUART 41 #define CFG_UART_PORT (0) 42 #define CONFIG_BAUDRATE 115200 43 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 44 45 #undef CONFIG_WATCHDOG 46 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 47 48 /* 49 * BOOTP options 50 */ 51 #define CONFIG_BOOTP_BOOTFILESIZE 52 #define CONFIG_BOOTP_BOOTPATH 53 #define CONFIG_BOOTP_GATEWAY 54 #define CONFIG_BOOTP_HOSTNAME 55 56 /* Command line configuration */ 57 #include <config_cmd_default.h> 58 59 #define CONFIG_CMD_BOOTD 60 #define CONFIG_CMD_CACHE 61 #define CONFIG_CMD_DHCP 62 #define CONFIG_CMD_ELF 63 #define CONFIG_CMD_FLASH 64 #define CONFIG_CMD_I2C 65 #define CONFIG_CMD_MEMORY 66 #define CONFIG_CMD_MISC 67 #define CONFIG_CMD_MII 68 #define CONFIG_CMD_NET 69 #define CONFIG_CMD_PCI 70 #define CONFIG_CMD_PING 71 #define CONFIG_CMD_REGINFO 72 73 #undef CONFIG_CMD_LOADB 74 #undef CONFIG_CMD_LOADS 75 76 #define CONFIG_MCFFEC 77 #ifdef CONFIG_MCFFEC 78 # define CONFIG_NET_MULTI 1 79 # define CONFIG_MII 1 80 # define CONFIG_MII_INIT 1 81 # define CFG_DISCOVER_PHY 82 # define CFG_RX_ETH_BUFFER 8 83 # define CFG_FAULT_ECHO_LINK_DOWN 84 85 # define CFG_FEC0_PINMUX 0 86 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 87 # define MCFFEC_TOUT_LOOP 50000 88 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 89 # ifndef CFG_DISCOVER_PHY 90 # define FECDUPLEX FULL 91 # define FECSPEED _100BASET 92 # else 93 # ifndef CFG_FAULT_ECHO_LINK_DOWN 94 # define CFG_FAULT_ECHO_LINK_DOWN 95 # endif 96 # endif /* CFG_DISCOVER_PHY */ 97 #endif 98 99 /* Timer */ 100 #define CONFIG_MCFTMR 101 #undef CONFIG_MCFPIT 102 103 /* I2C */ 104 #define CONFIG_FSL_I2C 105 #define CONFIG_HARD_I2C /* I2C with hw support */ 106 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 107 #define CFG_I2C_SPEED 80000 108 #define CFG_I2C_SLAVE 0x7F 109 #define CFG_I2C_OFFSET 0x00000300 110 #define CFG_IMMR CFG_MBAR 111 112 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 113 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 114 #define CONFIG_BOOTFILE "u-boot.bin" 115 #ifdef CONFIG_MCFFEC 116 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 117 # define CONFIG_IPADDR 192.162.1.2 118 # define CONFIG_NETMASK 255.255.255.0 119 # define CONFIG_SERVERIP 192.162.1.1 120 # define CONFIG_GATEWAYIP 192.162.1.1 121 # define CONFIG_OVERWRITE_ETHADDR_ONCE 122 #endif /* FEC_ENET */ 123 124 #define CONFIG_HOSTNAME M5235EVB 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "netdev=eth0\0" \ 127 "loadaddr=10000\0" \ 128 "u-boot=u-boot.bin\0" \ 129 "load=tftp ${loadaddr) ${u-boot}\0" \ 130 "upd=run load; run prog\0" \ 131 "prog=prot off ffe00000 ffe3ffff;" \ 132 "era ffe00000 ffe3ffff;" \ 133 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 134 "save\0" \ 135 "" 136 137 #define CONFIG_PRAM 512 /* 512 KB */ 138 #define CFG_PROMPT "-> " 139 #define CFG_LONGHELP /* undef to save memory */ 140 141 #if defined(CONFIG_KGDB) 142 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 143 #else 144 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 145 #endif 146 147 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 148 #define CFG_MAXARGS 16 /* max number of command args */ 149 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 150 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000) 151 152 #define CFG_HZ 1000 153 #define CFG_CLK 75000000 154 #define CFG_CPU_CLK CFG_CLK * 2 155 156 #define CFG_MBAR 0x40000000 157 158 /* 159 * Low Level Configuration Settings 160 * (address mappings, register initial values, etc.) 161 * You should know what you are doing if you make changes here. 162 */ 163 /*----------------------------------------------------------------------- 164 * Definitions for initial stack pointer and data area (in DPRAM) 165 */ 166 #define CFG_INIT_RAM_ADDR 0x20000000 167 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ 168 #define CFG_INIT_RAM_CTRL 0x21 169 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 170 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10) 171 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 172 173 /*----------------------------------------------------------------------- 174 * Start addresses for the final memory configuration 175 * (Set up by the startup code) 176 * Please note that CFG_SDRAM_BASE _must_ start at 0 177 */ 178 #define CFG_SDRAM_BASE 0x00000000 179 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ 180 181 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 182 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 183 184 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 185 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 186 187 #define CFG_BOOTPARAMS_LEN 64*1024 188 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 189 190 /* 191 * For booting Linux, the board info and command line data 192 * have to be in the first 8 MB of memory, since this is 193 * the maximum mapped by the Linux kernel during initialization ?? 194 */ 195 /* Initial Memory map for Linux */ 196 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 197 198 /*----------------------------------------------------------------------- 199 * FLASH organization 200 */ 201 #define CFG_FLASH_CFI 202 #ifdef CFG_FLASH_CFI 203 # define CFG_FLASH_CFI_DRIVER 1 204 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ 205 #ifdef NORFLASH_PS32BIT 206 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT 207 #else 208 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 209 #endif 210 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 211 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 212 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 213 #endif 214 215 #define CFG_FLASH_BASE (CFG_CS0_BASE << 16) 216 217 /* Configuration for environment 218 * Environment is embedded in u-boot in the second sector of the flash 219 */ 220 #define CFG_ENV_IS_IN_FLASH 1 221 #define CFG_ENV_IS_EMBEDDED 1 222 #ifdef NORFLASH_PS32BIT 223 # define CFG_ENV_OFFSET (0x8000) 224 # define CFG_ENV_SIZE 0x4000 225 # define CFG_ENV_SECT_SIZE 0x4000 226 #else 227 # define CFG_ENV_OFFSET (0x4000) 228 # define CFG_ENV_SIZE 0x2000 229 # define CFG_ENV_SECT_SIZE 0x2000 230 #endif 231 232 /*----------------------------------------------------------------------- 233 * Cache Configuration 234 */ 235 #define CFG_CACHELINE_SIZE 16 236 237 /*----------------------------------------------------------------------- 238 * Chipselect bank definitions 239 */ 240 /* 241 * CS0 - NOR Flash 1, 2, 4, or 8MB 242 * CS1 - Available 243 * CS2 - Available 244 * CS3 - Available 245 * CS4 - Available 246 * CS5 - Available 247 * CS6 - Available 248 * CS7 - Available 249 */ 250 #ifdef NORFLASH_PS32BIT 251 # define CFG_CS0_BASE 0xFFC0 252 # define CFG_CS0_MASK 0x003f0001 253 # define CFG_CS0_CTRL 0x1D00 254 #else 255 # define CFG_CS0_BASE 0xFFE0 256 # define CFG_CS0_MASK 0x001f0001 257 # define CFG_CS0_CTRL 0x1D80 258 #endif 259 260 #endif /* _M5329EVB_H */ 261