1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF523x /* define processor family */ 22 #define CONFIG_M5235 /* define processor type */ 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #include <config_cmd_default.h> 41 42 #define CONFIG_CMD_BOOTD 43 #define CONFIG_CMD_CACHE 44 #define CONFIG_CMD_DHCP 45 #define CONFIG_CMD_ELF 46 #define CONFIG_CMD_FLASH 47 #define CONFIG_CMD_I2C 48 #define CONFIG_CMD_MEMORY 49 #define CONFIG_CMD_MISC 50 #define CONFIG_CMD_MII 51 #define CONFIG_CMD_NET 52 #define CONFIG_CMD_PCI 53 #define CONFIG_CMD_PING 54 #define CONFIG_CMD_REGINFO 55 56 #undef CONFIG_CMD_LOADB 57 #undef CONFIG_CMD_LOADS 58 59 #define CONFIG_MCFFEC 60 #ifdef CONFIG_MCFFEC 61 # define CONFIG_MII 1 62 # define CONFIG_MII_INIT 1 63 # define CONFIG_SYS_DISCOVER_PHY 64 # define CONFIG_SYS_RX_ETH_BUFFER 8 65 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 67 # define CONFIG_SYS_FEC0_PINMUX 0 68 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 69 # define MCFFEC_TOUT_LOOP 50000 70 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 71 # ifndef CONFIG_SYS_DISCOVER_PHY 72 # define FECDUPLEX FULL 73 # define FECSPEED _100BASET 74 # else 75 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 77 # endif 78 # endif /* CONFIG_SYS_DISCOVER_PHY */ 79 #endif 80 81 /* Timer */ 82 #define CONFIG_MCFTMR 83 #undef CONFIG_MCFPIT 84 85 /* I2C */ 86 #define CONFIG_SYS_I2C 87 #define CONFIG_SYS_i2C_FSL 88 #define CONFIG_SYS_FSL_I2C_SPEED 80000 89 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 90 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 91 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 92 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 93 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 94 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 95 96 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 97 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 98 #define CONFIG_BOOTFILE "u-boot.bin" 99 #ifdef CONFIG_MCFFEC 100 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 101 # define CONFIG_IPADDR 192.162.1.2 102 # define CONFIG_NETMASK 255.255.255.0 103 # define CONFIG_SERVERIP 192.162.1.1 104 # define CONFIG_GATEWAYIP 192.162.1.1 105 # define CONFIG_OVERWRITE_ETHADDR_ONCE 106 #endif /* FEC_ENET */ 107 108 #define CONFIG_HOSTNAME M5235EVB 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 "netdev=eth0\0" \ 111 "loadaddr=10000\0" \ 112 "u-boot=u-boot.bin\0" \ 113 "load=tftp ${loadaddr) ${u-boot}\0" \ 114 "upd=run load; run prog\0" \ 115 "prog=prot off ffe00000 ffe3ffff;" \ 116 "era ffe00000 ffe3ffff;" \ 117 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 118 "save\0" \ 119 "" 120 121 #define CONFIG_PRAM 512 /* 512 KB */ 122 #define CONFIG_SYS_PROMPT "-> " 123 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 124 125 #if defined(CONFIG_KGDB) 126 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 127 #else 128 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 129 #endif 130 131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 132 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 134 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 135 136 #define CONFIG_SYS_HZ 1000 137 #define CONFIG_SYS_CLK 75000000 138 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 139 140 #define CONFIG_SYS_MBAR 0x40000000 141 142 /* 143 * Low Level Configuration Settings 144 * (address mappings, register initial values, etc.) 145 * You should know what you are doing if you make changes here. 146 */ 147 /*----------------------------------------------------------------------- 148 * Definitions for initial stack pointer and data area (in DPRAM) 149 */ 150 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 152 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 153 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 154 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 155 156 /*----------------------------------------------------------------------- 157 * Start addresses for the final memory configuration 158 * (Set up by the startup code) 159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 160 */ 161 #define CONFIG_SYS_SDRAM_BASE 0x00000000 162 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 163 164 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 165 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 166 167 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 168 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 169 170 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 171 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 172 173 /* 174 * For booting Linux, the board info and command line data 175 * have to be in the first 8 MB of memory, since this is 176 * the maximum mapped by the Linux kernel during initialization ?? 177 */ 178 /* Initial Memory map for Linux */ 179 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 180 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 181 182 /*----------------------------------------------------------------------- 183 * FLASH organization 184 */ 185 #define CONFIG_SYS_FLASH_CFI 186 #ifdef CONFIG_SYS_FLASH_CFI 187 # define CONFIG_FLASH_CFI_DRIVER 1 188 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 189 #ifdef NORFLASH_PS32BIT 190 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 191 #else 192 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 193 #endif 194 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 195 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 196 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 197 #endif 198 199 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 200 201 /* Configuration for environment 202 * Environment is embedded in u-boot in the second sector of the flash 203 */ 204 #define CONFIG_ENV_IS_IN_FLASH 1 205 #ifdef NORFLASH_PS32BIT 206 # define CONFIG_ENV_OFFSET (0x8000) 207 # define CONFIG_ENV_SIZE 0x4000 208 # define CONFIG_ENV_SECT_SIZE 0x4000 209 #else 210 # define CONFIG_ENV_OFFSET (0x4000) 211 # define CONFIG_ENV_SIZE 0x2000 212 # define CONFIG_ENV_SECT_SIZE 0x2000 213 #endif 214 215 /*----------------------------------------------------------------------- 216 * Cache Configuration 217 */ 218 #define CONFIG_SYS_CACHELINE_SIZE 16 219 220 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 221 CONFIG_SYS_INIT_RAM_SIZE - 8) 222 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 223 CONFIG_SYS_INIT_RAM_SIZE - 4) 224 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 225 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 226 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 227 CF_ACR_EN | CF_ACR_SM_ALL) 228 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 229 CF_CACR_CEIB | CF_CACR_DCM | \ 230 CF_CACR_EUSP) 231 232 /*----------------------------------------------------------------------- 233 * Chipselect bank definitions 234 */ 235 /* 236 * CS0 - NOR Flash 1, 2, 4, or 8MB 237 * CS1 - Available 238 * CS2 - Available 239 * CS3 - Available 240 * CS4 - Available 241 * CS5 - Available 242 * CS6 - Available 243 * CS7 - Available 244 */ 245 #ifdef NORFLASH_PS32BIT 246 # define CONFIG_SYS_CS0_BASE 0xFFC00000 247 # define CONFIG_SYS_CS0_MASK 0x003f0001 248 # define CONFIG_SYS_CS0_CTRL 0x00001D00 249 #else 250 # define CONFIG_SYS_CS0_BASE 0xFFE00000 251 # define CONFIG_SYS_CS0_MASK 0x001f0001 252 # define CONFIG_SYS_CS0_CTRL 0x00001D80 253 #endif 254 255 #endif /* _M5329EVB_H */ 256