1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 /* 29 * BOOTP options 30 */ 31 #define CONFIG_BOOTP_BOOTFILESIZE 32 #define CONFIG_BOOTP_BOOTPATH 33 #define CONFIG_BOOTP_GATEWAY 34 #define CONFIG_BOOTP_HOSTNAME 35 36 #define CONFIG_MCFFEC 37 #ifdef CONFIG_MCFFEC 38 # define CONFIG_MII 1 39 # define CONFIG_MII_INIT 1 40 # define CONFIG_SYS_DISCOVER_PHY 41 # define CONFIG_SYS_RX_ETH_BUFFER 8 42 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43 44 # define CONFIG_SYS_FEC0_PINMUX 0 45 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 46 # define MCFFEC_TOUT_LOOP 50000 47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 48 # ifndef CONFIG_SYS_DISCOVER_PHY 49 # define FECDUPLEX FULL 50 # define FECSPEED _100BASET 51 # else 52 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # endif 55 # endif /* CONFIG_SYS_DISCOVER_PHY */ 56 #endif 57 58 /* Timer */ 59 #define CONFIG_MCFTMR 60 #undef CONFIG_MCFPIT 61 62 /* I2C */ 63 #define CONFIG_SYS_I2C 64 #define CONFIG_SYS_i2C_FSL 65 #define CONFIG_SYS_FSL_I2C_SPEED 80000 66 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 67 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 68 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 69 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 70 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 71 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 72 73 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 74 #define CONFIG_BOOTFILE "u-boot.bin" 75 #ifdef CONFIG_MCFFEC 76 # define CONFIG_IPADDR 192.162.1.2 77 # define CONFIG_NETMASK 255.255.255.0 78 # define CONFIG_SERVERIP 192.162.1.1 79 # define CONFIG_GATEWAYIP 192.162.1.1 80 #endif /* FEC_ENET */ 81 82 #define CONFIG_HOSTNAME M5235EVB 83 #define CONFIG_EXTRA_ENV_SETTINGS \ 84 "netdev=eth0\0" \ 85 "loadaddr=10000\0" \ 86 "u-boot=u-boot.bin\0" \ 87 "load=tftp ${loadaddr) ${u-boot}\0" \ 88 "upd=run load; run prog\0" \ 89 "prog=prot off ffe00000 ffe3ffff;" \ 90 "era ffe00000 ffe3ffff;" \ 91 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 92 "save\0" \ 93 "" 94 95 #define CONFIG_PRAM 512 /* 512 KB */ 96 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 97 98 #if defined(CONFIG_KGDB) 99 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 100 #else 101 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 102 #endif 103 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 105 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 106 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 107 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 108 109 #define CONFIG_SYS_CLK 75000000 110 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 111 112 #define CONFIG_SYS_MBAR 0x40000000 113 114 /* 115 * Low Level Configuration Settings 116 * (address mappings, register initial values, etc.) 117 * You should know what you are doing if you make changes here. 118 */ 119 /*----------------------------------------------------------------------- 120 * Definitions for initial stack pointer and data area (in DPRAM) 121 */ 122 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 123 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 124 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 125 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 126 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 127 128 /*----------------------------------------------------------------------- 129 * Start addresses for the final memory configuration 130 * (Set up by the startup code) 131 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 132 */ 133 #define CONFIG_SYS_SDRAM_BASE 0x00000000 134 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 135 136 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 137 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 138 139 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 140 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 141 142 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 143 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 144 145 /* 146 * For booting Linux, the board info and command line data 147 * have to be in the first 8 MB of memory, since this is 148 * the maximum mapped by the Linux kernel during initialization ?? 149 */ 150 /* Initial Memory map for Linux */ 151 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 152 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 153 154 /*----------------------------------------------------------------------- 155 * FLASH organization 156 */ 157 #define CONFIG_SYS_FLASH_CFI 158 #ifdef CONFIG_SYS_FLASH_CFI 159 # define CONFIG_FLASH_CFI_DRIVER 1 160 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 161 #ifdef NORFLASH_PS32BIT 162 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 163 #else 164 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 165 #endif 166 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 167 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 168 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 169 #endif 170 171 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 172 173 /* Configuration for environment 174 * Environment is embedded in u-boot in the second sector of the flash 175 */ 176 177 #define LDS_BOARD_TEXT \ 178 . = DEFINED(env_offset) ? env_offset : .; \ 179 common/env_embedded.o (.text); 180 181 #ifdef NORFLASH_PS32BIT 182 # define CONFIG_ENV_OFFSET (0x8000) 183 # define CONFIG_ENV_SIZE 0x4000 184 # define CONFIG_ENV_SECT_SIZE 0x4000 185 #else 186 # define CONFIG_ENV_OFFSET (0x4000) 187 # define CONFIG_ENV_SIZE 0x2000 188 # define CONFIG_ENV_SECT_SIZE 0x2000 189 #endif 190 191 /*----------------------------------------------------------------------- 192 * Cache Configuration 193 */ 194 #define CONFIG_SYS_CACHELINE_SIZE 16 195 196 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 197 CONFIG_SYS_INIT_RAM_SIZE - 8) 198 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 199 CONFIG_SYS_INIT_RAM_SIZE - 4) 200 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 201 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 202 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 203 CF_ACR_EN | CF_ACR_SM_ALL) 204 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 205 CF_CACR_CEIB | CF_CACR_DCM | \ 206 CF_CACR_EUSP) 207 208 /*----------------------------------------------------------------------- 209 * Chipselect bank definitions 210 */ 211 /* 212 * CS0 - NOR Flash 1, 2, 4, or 8MB 213 * CS1 - Available 214 * CS2 - Available 215 * CS3 - Available 216 * CS4 - Available 217 * CS5 - Available 218 * CS6 - Available 219 * CS7 - Available 220 */ 221 #ifdef NORFLASH_PS32BIT 222 # define CONFIG_SYS_CS0_BASE 0xFFC00000 223 # define CONFIG_SYS_CS0_MASK 0x003f0001 224 # define CONFIG_SYS_CS0_CTRL 0x00001D00 225 #else 226 # define CONFIG_SYS_CS0_BASE 0xFFE00000 227 # define CONFIG_SYS_CS0_MASK 0x001f0001 228 # define CONFIG_SYS_CS0_CTRL 0x00001D80 229 #endif 230 231 #endif /* _M5329EVB_H */ 232