1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 /* 29 * BOOTP options 30 */ 31 #define CONFIG_BOOTP_BOOTFILESIZE 32 #define CONFIG_BOOTP_BOOTPATH 33 #define CONFIG_BOOTP_GATEWAY 34 #define CONFIG_BOOTP_HOSTNAME 35 36 /* Command line configuration */ 37 #define CONFIG_CMD_PCI 38 #define CONFIG_CMD_REGINFO 39 40 #define CONFIG_MCFFEC 41 #ifdef CONFIG_MCFFEC 42 # define CONFIG_MII 1 43 # define CONFIG_MII_INIT 1 44 # define CONFIG_SYS_DISCOVER_PHY 45 # define CONFIG_SYS_RX_ETH_BUFFER 8 46 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 48 # define CONFIG_SYS_FEC0_PINMUX 0 49 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 50 # define MCFFEC_TOUT_LOOP 50000 51 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 52 # ifndef CONFIG_SYS_DISCOVER_PHY 53 # define FECDUPLEX FULL 54 # define FECSPEED _100BASET 55 # else 56 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 58 # endif 59 # endif /* CONFIG_SYS_DISCOVER_PHY */ 60 #endif 61 62 /* Timer */ 63 #define CONFIG_MCFTMR 64 #undef CONFIG_MCFPIT 65 66 /* I2C */ 67 #define CONFIG_SYS_I2C 68 #define CONFIG_SYS_i2C_FSL 69 #define CONFIG_SYS_FSL_I2C_SPEED 80000 70 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 71 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 72 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 73 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 74 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 75 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 76 77 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 78 #define CONFIG_BOOTFILE "u-boot.bin" 79 #ifdef CONFIG_MCFFEC 80 # define CONFIG_IPADDR 192.162.1.2 81 # define CONFIG_NETMASK 255.255.255.0 82 # define CONFIG_SERVERIP 192.162.1.1 83 # define CONFIG_GATEWAYIP 192.162.1.1 84 #endif /* FEC_ENET */ 85 86 #define CONFIG_HOSTNAME M5235EVB 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 "netdev=eth0\0" \ 89 "loadaddr=10000\0" \ 90 "u-boot=u-boot.bin\0" \ 91 "load=tftp ${loadaddr) ${u-boot}\0" \ 92 "upd=run load; run prog\0" \ 93 "prog=prot off ffe00000 ffe3ffff;" \ 94 "era ffe00000 ffe3ffff;" \ 95 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 96 "save\0" \ 97 "" 98 99 #define CONFIG_PRAM 512 /* 512 KB */ 100 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 101 102 #if defined(CONFIG_KGDB) 103 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 104 #else 105 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 #endif 107 108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 109 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 111 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 112 113 #define CONFIG_SYS_CLK 75000000 114 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 115 116 #define CONFIG_SYS_MBAR 0x40000000 117 118 /* 119 * Low Level Configuration Settings 120 * (address mappings, register initial values, etc.) 121 * You should know what you are doing if you make changes here. 122 */ 123 /*----------------------------------------------------------------------- 124 * Definitions for initial stack pointer and data area (in DPRAM) 125 */ 126 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 127 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 128 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 129 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 130 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 131 132 /*----------------------------------------------------------------------- 133 * Start addresses for the final memory configuration 134 * (Set up by the startup code) 135 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 136 */ 137 #define CONFIG_SYS_SDRAM_BASE 0x00000000 138 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 139 140 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 141 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 142 143 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 144 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 145 146 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 147 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 148 149 /* 150 * For booting Linux, the board info and command line data 151 * have to be in the first 8 MB of memory, since this is 152 * the maximum mapped by the Linux kernel during initialization ?? 153 */ 154 /* Initial Memory map for Linux */ 155 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 156 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 157 158 /*----------------------------------------------------------------------- 159 * FLASH organization 160 */ 161 #define CONFIG_SYS_FLASH_CFI 162 #ifdef CONFIG_SYS_FLASH_CFI 163 # define CONFIG_FLASH_CFI_DRIVER 1 164 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 165 #ifdef NORFLASH_PS32BIT 166 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 167 #else 168 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 169 #endif 170 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 171 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 172 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 173 #endif 174 175 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 176 177 /* Configuration for environment 178 * Environment is embedded in u-boot in the second sector of the flash 179 */ 180 #define CONFIG_ENV_IS_IN_FLASH 1 181 182 #define LDS_BOARD_TEXT \ 183 . = DEFINED(env_offset) ? env_offset : .; \ 184 common/env_embedded.o (.text); 185 186 #ifdef NORFLASH_PS32BIT 187 # define CONFIG_ENV_OFFSET (0x8000) 188 # define CONFIG_ENV_SIZE 0x4000 189 # define CONFIG_ENV_SECT_SIZE 0x4000 190 #else 191 # define CONFIG_ENV_OFFSET (0x4000) 192 # define CONFIG_ENV_SIZE 0x2000 193 # define CONFIG_ENV_SECT_SIZE 0x2000 194 #endif 195 196 /*----------------------------------------------------------------------- 197 * Cache Configuration 198 */ 199 #define CONFIG_SYS_CACHELINE_SIZE 16 200 201 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 202 CONFIG_SYS_INIT_RAM_SIZE - 8) 203 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 204 CONFIG_SYS_INIT_RAM_SIZE - 4) 205 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 206 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 207 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 208 CF_ACR_EN | CF_ACR_SM_ALL) 209 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 210 CF_CACR_CEIB | CF_CACR_DCM | \ 211 CF_CACR_EUSP) 212 213 /*----------------------------------------------------------------------- 214 * Chipselect bank definitions 215 */ 216 /* 217 * CS0 - NOR Flash 1, 2, 4, or 8MB 218 * CS1 - Available 219 * CS2 - Available 220 * CS3 - Available 221 * CS4 - Available 222 * CS5 - Available 223 * CS6 - Available 224 * CS7 - Available 225 */ 226 #ifdef NORFLASH_PS32BIT 227 # define CONFIG_SYS_CS0_BASE 0xFFC00000 228 # define CONFIG_SYS_CS0_MASK 0x003f0001 229 # define CONFIG_SYS_CS0_CTRL 0x00001D00 230 #else 231 # define CONFIG_SYS_CS0_BASE 0xFFE00000 232 # define CONFIG_SYS_CS0_MASK 0x001f0001 233 # define CONFIG_SYS_CS0_CTRL 0x00001D80 234 #endif 235 236 #endif /* _M5329EVB_H */ 237