1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* 30 * BOOTP options 31 */ 32 #define CONFIG_BOOTP_BOOTFILESIZE 33 #define CONFIG_BOOTP_BOOTPATH 34 #define CONFIG_BOOTP_GATEWAY 35 #define CONFIG_BOOTP_HOSTNAME 36 37 /* Command line configuration */ 38 #define CONFIG_CMD_CACHE 39 #define CONFIG_CMD_DHCP 40 #define CONFIG_CMD_I2C 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_PCI 43 #define CONFIG_CMD_PING 44 #define CONFIG_CMD_REGINFO 45 46 47 #define CONFIG_MCFFEC 48 #ifdef CONFIG_MCFFEC 49 # define CONFIG_MII 1 50 # define CONFIG_MII_INIT 1 51 # define CONFIG_SYS_DISCOVER_PHY 52 # define CONFIG_SYS_RX_ETH_BUFFER 8 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 55 # define CONFIG_SYS_FEC0_PINMUX 0 56 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 57 # define MCFFEC_TOUT_LOOP 50000 58 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 59 # ifndef CONFIG_SYS_DISCOVER_PHY 60 # define FECDUPLEX FULL 61 # define FECSPEED _100BASET 62 # else 63 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 65 # endif 66 # endif /* CONFIG_SYS_DISCOVER_PHY */ 67 #endif 68 69 /* Timer */ 70 #define CONFIG_MCFTMR 71 #undef CONFIG_MCFPIT 72 73 /* I2C */ 74 #define CONFIG_SYS_I2C 75 #define CONFIG_SYS_i2C_FSL 76 #define CONFIG_SYS_FSL_I2C_SPEED 80000 77 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 78 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 79 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 80 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 81 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 82 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 83 84 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 85 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 86 #define CONFIG_BOOTFILE "u-boot.bin" 87 #ifdef CONFIG_MCFFEC 88 # define CONFIG_IPADDR 192.162.1.2 89 # define CONFIG_NETMASK 255.255.255.0 90 # define CONFIG_SERVERIP 192.162.1.1 91 # define CONFIG_GATEWAYIP 192.162.1.1 92 #endif /* FEC_ENET */ 93 94 #define CONFIG_HOSTNAME M5235EVB 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 "netdev=eth0\0" \ 97 "loadaddr=10000\0" \ 98 "u-boot=u-boot.bin\0" \ 99 "load=tftp ${loadaddr) ${u-boot}\0" \ 100 "upd=run load; run prog\0" \ 101 "prog=prot off ffe00000 ffe3ffff;" \ 102 "era ffe00000 ffe3ffff;" \ 103 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 104 "save\0" \ 105 "" 106 107 #define CONFIG_PRAM 512 /* 512 KB */ 108 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 109 110 #if defined(CONFIG_KGDB) 111 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 112 #else 113 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 114 #endif 115 116 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 117 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 119 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 120 121 #define CONFIG_SYS_CLK 75000000 122 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 123 124 #define CONFIG_SYS_MBAR 0x40000000 125 126 /* 127 * Low Level Configuration Settings 128 * (address mappings, register initial values, etc.) 129 * You should know what you are doing if you make changes here. 130 */ 131 /*----------------------------------------------------------------------- 132 * Definitions for initial stack pointer and data area (in DPRAM) 133 */ 134 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 135 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 136 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 137 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 138 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 139 140 /*----------------------------------------------------------------------- 141 * Start addresses for the final memory configuration 142 * (Set up by the startup code) 143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 144 */ 145 #define CONFIG_SYS_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 147 148 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 149 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 150 151 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 152 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 153 154 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 155 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 156 157 /* 158 * For booting Linux, the board info and command line data 159 * have to be in the first 8 MB of memory, since this is 160 * the maximum mapped by the Linux kernel during initialization ?? 161 */ 162 /* Initial Memory map for Linux */ 163 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 164 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 165 166 /*----------------------------------------------------------------------- 167 * FLASH organization 168 */ 169 #define CONFIG_SYS_FLASH_CFI 170 #ifdef CONFIG_SYS_FLASH_CFI 171 # define CONFIG_FLASH_CFI_DRIVER 1 172 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 173 #ifdef NORFLASH_PS32BIT 174 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 175 #else 176 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 177 #endif 178 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 179 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 180 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 181 #endif 182 183 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 184 185 /* Configuration for environment 186 * Environment is embedded in u-boot in the second sector of the flash 187 */ 188 #define CONFIG_ENV_IS_IN_FLASH 1 189 190 #define LDS_BOARD_TEXT \ 191 . = DEFINED(env_offset) ? env_offset : .; \ 192 common/env_embedded.o (.text); 193 194 #ifdef NORFLASH_PS32BIT 195 # define CONFIG_ENV_OFFSET (0x8000) 196 # define CONFIG_ENV_SIZE 0x4000 197 # define CONFIG_ENV_SECT_SIZE 0x4000 198 #else 199 # define CONFIG_ENV_OFFSET (0x4000) 200 # define CONFIG_ENV_SIZE 0x2000 201 # define CONFIG_ENV_SECT_SIZE 0x2000 202 #endif 203 204 /*----------------------------------------------------------------------- 205 * Cache Configuration 206 */ 207 #define CONFIG_SYS_CACHELINE_SIZE 16 208 209 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 210 CONFIG_SYS_INIT_RAM_SIZE - 8) 211 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 212 CONFIG_SYS_INIT_RAM_SIZE - 4) 213 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 214 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 215 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 216 CF_ACR_EN | CF_ACR_SM_ALL) 217 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 218 CF_CACR_CEIB | CF_CACR_DCM | \ 219 CF_CACR_EUSP) 220 221 /*----------------------------------------------------------------------- 222 * Chipselect bank definitions 223 */ 224 /* 225 * CS0 - NOR Flash 1, 2, 4, or 8MB 226 * CS1 - Available 227 * CS2 - Available 228 * CS3 - Available 229 * CS4 - Available 230 * CS5 - Available 231 * CS6 - Available 232 * CS7 - Available 233 */ 234 #ifdef NORFLASH_PS32BIT 235 # define CONFIG_SYS_CS0_BASE 0xFFC00000 236 # define CONFIG_SYS_CS0_MASK 0x003f0001 237 # define CONFIG_SYS_CS0_CTRL 0x00001D00 238 #else 239 # define CONFIG_SYS_CS0_BASE 0xFFE00000 240 # define CONFIG_SYS_CS0_MASK 0x001f0001 241 # define CONFIG_SYS_CS0_CTRL 0x00001D80 242 #endif 243 244 #endif /* _M5329EVB_H */ 245