1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M52277EVB /* M52277EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #define CONFIG_CMD_JFFS2 40 #define CONFIG_CMD_REGINFO 41 42 #define CONFIG_HOSTNAME M52277EVB 43 #define CONFIG_SYS_UBOOT_END 0x3FFFF 44 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 45 #ifdef CONFIG_SYS_STMICRO_BOOT 46 /* ST Micro serial flash */ 47 #define CONFIG_EXTRA_ENV_SETTINGS \ 48 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 49 "loadaddr=0x40010000\0" \ 50 "uboot=u-boot.bin\0" \ 51 "load=loadb ${loadaddr} ${baudrate};" \ 52 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 53 "upd=run load; run prog\0" \ 54 "prog=sf probe 0:2 10000 1;" \ 55 "sf erase 0 30000;" \ 56 "sf write ${loadaddr} 0 30000;" \ 57 "save\0" \ 58 "" 59 #endif 60 #ifdef CONFIG_SYS_SPANSION_BOOT 61 #define CONFIG_EXTRA_ENV_SETTINGS \ 62 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 63 "loadaddr=0x40010000\0" \ 64 "uboot=u-boot.bin\0" \ 65 "load=loadb ${loadaddr} ${baudrate}\0" \ 66 "upd=run load; run prog\0" \ 67 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 68 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 69 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 70 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 71 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 72 " ${filesize}; save\0" \ 73 "updsbf=run loadsbf; run progsbf\0" \ 74 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 75 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 76 "progsbf=sf probe 0:2 10000 1;" \ 77 "sf erase 0 30000;" \ 78 "sf write ${loadaddr} 0 30000;" \ 79 "" 80 #endif 81 82 /* LCD */ 83 #ifdef CONFIG_CMD_BMP 84 #define CONFIG_SPLASH_SCREEN 85 #define CONFIG_LCD_LOGO 86 #define CONFIG_SHARP_LQ035Q7DH06 87 #endif 88 89 /* USB */ 90 #ifdef CONFIG_CMD_USB 91 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 92 #define CONFIG_SYS_USB_EHCI_CPU_INIT 93 #endif 94 95 /* Realtime clock */ 96 #define CONFIG_MCFRTC 97 #undef RTC_DEBUG 98 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 99 100 /* Timer */ 101 #define CONFIG_MCFTMR 102 #undef CONFIG_MCFPIT 103 104 /* I2c */ 105 #define CONFIG_SYS_I2C 106 #define CONFIG_SYS_I2C_FSL 107 #define CONFIG_SYS_FSL_I2C_SPEED 80000 108 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 109 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 110 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 111 112 /* DSPI and Serial Flash */ 113 #define CONFIG_CF_SPI 114 #define CONFIG_CF_DSPI 115 #define CONFIG_HARD_SPI 116 #define CONFIG_SYS_SBFHDR_SIZE 0x7 117 #ifdef CONFIG_CMD_SPI 118 # define CONFIG_SYS_DSPI_CS2 119 120 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 121 DSPI_CTAR_PCSSCK_1CLK | \ 122 DSPI_CTAR_PASC(0) | \ 123 DSPI_CTAR_PDT(0) | \ 124 DSPI_CTAR_CSSCK(0) | \ 125 DSPI_CTAR_ASC(0) | \ 126 DSPI_CTAR_DT(1)) 127 #endif 128 129 /* Input, PCI, Flexbus, and VCO */ 130 #define CONFIG_EXTRA_CLOCK 131 132 #define CONFIG_SYS_INPUT_CLKSRC 16000000 133 134 #define CONFIG_PRAM 2048 /* 2048 KB */ 135 136 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 137 138 #if defined(CONFIG_CMD_KGDB) 139 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 140 #else 141 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 142 #endif 143 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 144 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 145 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 146 147 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 148 149 #define CONFIG_SYS_MBAR 0xFC000000 150 151 /* 152 * Low Level Configuration Settings 153 * (address mappings, register initial values, etc.) 154 * You should know what you are doing if you make changes here. 155 */ 156 157 /* 158 * Definitions for initial stack pointer and data area (in DPRAM) 159 */ 160 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 161 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 162 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 163 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 164 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 165 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 166 167 /* 168 * Start addresses for the final memory configuration 169 * (Set up by the startup code) 170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 171 */ 172 #define CONFIG_SYS_SDRAM_BASE 0x40000000 173 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 174 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 175 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 176 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 177 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 178 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 179 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 180 181 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 182 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 183 184 #ifdef CONFIG_CF_SBF 185 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 186 #else 187 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 188 #endif 189 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 190 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 191 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 192 193 /* Initial Memory map for Linux */ 194 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 195 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 196 197 /* 198 * Configuration for environment 199 * Environment is not embedded in u-boot. First time runing may have env 200 * crc error warning if there is no correct environment on the flash. 201 */ 202 #ifdef CONFIG_CF_SBF 203 # define CONFIG_ENV_IS_IN_SPI_FLASH 204 # define CONFIG_ENV_SPI_CS 2 205 #else 206 # define CONFIG_ENV_IS_IN_FLASH 1 207 #endif 208 #define CONFIG_ENV_OVERWRITE 1 209 210 /*----------------------------------------------------------------------- 211 * FLASH organization 212 */ 213 #ifdef CONFIG_SYS_STMICRO_BOOT 214 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 215 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 216 # define CONFIG_ENV_OFFSET 0x30000 217 # define CONFIG_ENV_SIZE 0x1000 218 # define CONFIG_ENV_SECT_SIZE 0x10000 219 #endif 220 #ifdef CONFIG_SYS_SPANSION_BOOT 221 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 222 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 223 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 224 # define CONFIG_ENV_SIZE 0x1000 225 # define CONFIG_ENV_SECT_SIZE 0x8000 226 #endif 227 228 #define CONFIG_SYS_FLASH_CFI 229 #ifdef CONFIG_SYS_FLASH_CFI 230 # define CONFIG_FLASH_CFI_DRIVER 1 231 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 232 # define CONFIG_FLASH_SPANSION_S29WS_N 1 233 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 234 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 235 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 236 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 237 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 238 # define CONFIG_SYS_FLASH_CHECKSUM 239 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 240 #endif 241 242 #define LDS_BOARD_TEXT \ 243 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 244 arch/m68k/lib/built-in.o (.text*) 245 246 /* 247 * This is setting for JFFS2 support in u-boot. 248 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 249 */ 250 #ifdef CONFIG_CMD_JFFS2 251 # define CONFIG_JFFS2_DEV "nor0" 252 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 253 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 254 #endif 255 256 /*----------------------------------------------------------------------- 257 * Cache Configuration 258 */ 259 #define CONFIG_SYS_CACHELINE_SIZE 16 260 261 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 262 CONFIG_SYS_INIT_RAM_SIZE - 8) 263 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 264 CONFIG_SYS_INIT_RAM_SIZE - 4) 265 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 266 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 267 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 268 CF_ACR_EN | CF_ACR_SM_ALL) 269 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 270 CF_CACR_DISD | CF_CACR_INVI | \ 271 CF_CACR_CEIB | CF_CACR_DCM | \ 272 CF_CACR_EUSP) 273 274 /*----------------------------------------------------------------------- 275 * Memory bank definitions 276 */ 277 /* 278 * CS0 - NOR Flash 279 * CS1 - Available 280 * CS2 - Available 281 * CS3 - Available 282 * CS4 - Available 283 * CS5 - Available 284 */ 285 286 #ifdef CONFIG_CF_SBF 287 #define CONFIG_SYS_CS0_BASE 0x04000000 288 #define CONFIG_SYS_CS0_MASK 0x00FF0001 289 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 290 #else 291 #define CONFIG_SYS_CS0_BASE 0x00000000 292 #define CONFIG_SYS_CS0_MASK 0x00FF0001 293 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 294 #endif 295 296 #endif /* _M52277EVB_H */ 297