1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M52277EVB /* M52277EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #define CONFIG_CMD_DATE 41 #define CONFIG_CMD_JFFS2 42 #define CONFIG_CMD_REGINFO 43 #undef CONFIG_CMD_BMP 44 45 #define CONFIG_HOSTNAME M52277EVB 46 #define CONFIG_SYS_UBOOT_END 0x3FFFF 47 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 48 #ifdef CONFIG_SYS_STMICRO_BOOT 49 /* ST Micro serial flash */ 50 #define CONFIG_EXTRA_ENV_SETTINGS \ 51 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 52 "loadaddr=0x40010000\0" \ 53 "uboot=u-boot.bin\0" \ 54 "load=loadb ${loadaddr} ${baudrate};" \ 55 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 56 "upd=run load; run prog\0" \ 57 "prog=sf probe 0:2 10000 1;" \ 58 "sf erase 0 30000;" \ 59 "sf write ${loadaddr} 0 30000;" \ 60 "save\0" \ 61 "" 62 #endif 63 #ifdef CONFIG_SYS_SPANSION_BOOT 64 #define CONFIG_EXTRA_ENV_SETTINGS \ 65 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 66 "loadaddr=0x40010000\0" \ 67 "uboot=u-boot.bin\0" \ 68 "load=loadb ${loadaddr} ${baudrate}\0" \ 69 "upd=run load; run prog\0" \ 70 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 71 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 72 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 73 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 74 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 75 " ${filesize}; save\0" \ 76 "updsbf=run loadsbf; run progsbf\0" \ 77 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 78 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 79 "progsbf=sf probe 0:2 10000 1;" \ 80 "sf erase 0 30000;" \ 81 "sf write ${loadaddr} 0 30000;" \ 82 "" 83 #endif 84 85 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 86 /* LCD */ 87 #ifdef CONFIG_CMD_BMP 88 #define CONFIG_LCD 89 #define CONFIG_SPLASH_SCREEN 90 #define CONFIG_LCD_LOGO 91 #define CONFIG_SHARP_LQ035Q7DH06 92 #endif 93 94 /* USB */ 95 #ifdef CONFIG_CMD_USB 96 #define CONFIG_USB_EHCI 97 #define CONFIG_USB_STORAGE 98 #define CONFIG_DOS_PARTITION 99 #define CONFIG_MAC_PARTITION 100 #define CONFIG_ISO_PARTITION 101 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 102 #define CONFIG_SYS_USB_EHCI_CPU_INIT 103 #endif 104 105 /* Realtime clock */ 106 #define CONFIG_MCFRTC 107 #undef RTC_DEBUG 108 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 109 110 /* Timer */ 111 #define CONFIG_MCFTMR 112 #undef CONFIG_MCFPIT 113 114 /* I2c */ 115 #define CONFIG_SYS_I2C 116 #define CONFIG_SYS_I2C_FSL 117 #define CONFIG_SYS_FSL_I2C_SPEED 80000 118 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 119 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 120 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 121 122 /* DSPI and Serial Flash */ 123 #define CONFIG_CF_SPI 124 #define CONFIG_CF_DSPI 125 #define CONFIG_HARD_SPI 126 #define CONFIG_SYS_SBFHDR_SIZE 0x7 127 #ifdef CONFIG_CMD_SPI 128 # define CONFIG_SYS_DSPI_CS2 129 130 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 131 DSPI_CTAR_PCSSCK_1CLK | \ 132 DSPI_CTAR_PASC(0) | \ 133 DSPI_CTAR_PDT(0) | \ 134 DSPI_CTAR_CSSCK(0) | \ 135 DSPI_CTAR_ASC(0) | \ 136 DSPI_CTAR_DT(1)) 137 #endif 138 139 /* Input, PCI, Flexbus, and VCO */ 140 #define CONFIG_EXTRA_CLOCK 141 142 #define CONFIG_SYS_INPUT_CLKSRC 16000000 143 144 #define CONFIG_PRAM 2048 /* 2048 KB */ 145 146 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 147 148 #if defined(CONFIG_CMD_KGDB) 149 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 150 #else 151 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 152 #endif 153 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 154 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 155 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 156 157 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 158 159 #define CONFIG_SYS_MBAR 0xFC000000 160 161 /* 162 * Low Level Configuration Settings 163 * (address mappings, register initial values, etc.) 164 * You should know what you are doing if you make changes here. 165 */ 166 167 /* 168 * Definitions for initial stack pointer and data area (in DPRAM) 169 */ 170 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 171 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 172 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 173 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 174 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 175 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 176 177 /* 178 * Start addresses for the final memory configuration 179 * (Set up by the startup code) 180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 181 */ 182 #define CONFIG_SYS_SDRAM_BASE 0x40000000 183 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 184 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 185 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 186 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 187 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 188 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 189 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 190 191 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 192 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 193 194 #ifdef CONFIG_CF_SBF 195 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 196 #else 197 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 198 #endif 199 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 200 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 201 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 202 203 /* Initial Memory map for Linux */ 204 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 205 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 206 207 /* 208 * Configuration for environment 209 * Environment is not embedded in u-boot. First time runing may have env 210 * crc error warning if there is no correct environment on the flash. 211 */ 212 #ifdef CONFIG_CF_SBF 213 # define CONFIG_ENV_IS_IN_SPI_FLASH 214 # define CONFIG_ENV_SPI_CS 2 215 #else 216 # define CONFIG_ENV_IS_IN_FLASH 1 217 #endif 218 #define CONFIG_ENV_OVERWRITE 1 219 220 /*----------------------------------------------------------------------- 221 * FLASH organization 222 */ 223 #ifdef CONFIG_SYS_STMICRO_BOOT 224 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 225 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 226 # define CONFIG_ENV_OFFSET 0x30000 227 # define CONFIG_ENV_SIZE 0x1000 228 # define CONFIG_ENV_SECT_SIZE 0x10000 229 #endif 230 #ifdef CONFIG_SYS_SPANSION_BOOT 231 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 232 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 233 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 234 # define CONFIG_ENV_SIZE 0x1000 235 # define CONFIG_ENV_SECT_SIZE 0x8000 236 #endif 237 238 #define CONFIG_SYS_FLASH_CFI 239 #ifdef CONFIG_SYS_FLASH_CFI 240 # define CONFIG_FLASH_CFI_DRIVER 1 241 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 242 # define CONFIG_FLASH_SPANSION_S29WS_N 1 243 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 244 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 245 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 246 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 247 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 248 # define CONFIG_SYS_FLASH_CHECKSUM 249 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 250 #endif 251 252 #define LDS_BOARD_TEXT \ 253 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 254 arch/m68k/lib/built-in.o (.text*) 255 256 /* 257 * This is setting for JFFS2 support in u-boot. 258 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 259 */ 260 #ifdef CONFIG_CMD_JFFS2 261 # define CONFIG_JFFS2_DEV "nor0" 262 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 263 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 264 #endif 265 266 /*----------------------------------------------------------------------- 267 * Cache Configuration 268 */ 269 #define CONFIG_SYS_CACHELINE_SIZE 16 270 271 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 272 CONFIG_SYS_INIT_RAM_SIZE - 8) 273 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 274 CONFIG_SYS_INIT_RAM_SIZE - 4) 275 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 276 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 277 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 278 CF_ACR_EN | CF_ACR_SM_ALL) 279 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 280 CF_CACR_DISD | CF_CACR_INVI | \ 281 CF_CACR_CEIB | CF_CACR_DCM | \ 282 CF_CACR_EUSP) 283 284 /*----------------------------------------------------------------------- 285 * Memory bank definitions 286 */ 287 /* 288 * CS0 - NOR Flash 289 * CS1 - Available 290 * CS2 - Available 291 * CS3 - Available 292 * CS4 - Available 293 * CS5 - Available 294 */ 295 296 #ifdef CONFIG_CF_SBF 297 #define CONFIG_SYS_CS0_BASE 0x04000000 298 #define CONFIG_SYS_CS0_MASK 0x00FF0001 299 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 300 #else 301 #define CONFIG_SYS_CS0_BASE 0x00000000 302 #define CONFIG_SYS_CS0_MASK 0x00FF0001 303 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 304 #endif 305 306 #endif /* _M52277EVB_H */ 307