1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 27 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 28 29 /* 30 * BOOTP options 31 */ 32 #define CONFIG_BOOTP_BOOTFILESIZE 33 34 #define CONFIG_HOSTNAME M52277EVB 35 #define CONFIG_SYS_UBOOT_END 0x3FFFF 36 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 37 #ifdef CONFIG_SYS_STMICRO_BOOT 38 /* ST Micro serial flash */ 39 #define CONFIG_EXTRA_ENV_SETTINGS \ 40 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 41 "loadaddr=0x40010000\0" \ 42 "uboot=u-boot.bin\0" \ 43 "load=loadb ${loadaddr} ${baudrate};" \ 44 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 45 "upd=run load; run prog\0" \ 46 "prog=sf probe 0:2 10000 1;" \ 47 "sf erase 0 30000;" \ 48 "sf write ${loadaddr} 0 30000;" \ 49 "save\0" \ 50 "" 51 #endif 52 #ifdef CONFIG_SYS_SPANSION_BOOT 53 #define CONFIG_EXTRA_ENV_SETTINGS \ 54 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 55 "loadaddr=0x40010000\0" \ 56 "uboot=u-boot.bin\0" \ 57 "load=loadb ${loadaddr} ${baudrate}\0" \ 58 "upd=run load; run prog\0" \ 59 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 60 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 61 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 62 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 63 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 64 " ${filesize}; save\0" \ 65 "updsbf=run loadsbf; run progsbf\0" \ 66 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 67 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 68 "progsbf=sf probe 0:2 10000 1;" \ 69 "sf erase 0 30000;" \ 70 "sf write ${loadaddr} 0 30000;" \ 71 "" 72 #endif 73 74 /* LCD */ 75 #ifdef CONFIG_CMD_BMP 76 #define CONFIG_SPLASH_SCREEN 77 #define CONFIG_LCD_LOGO 78 #define CONFIG_SHARP_LQ035Q7DH06 79 #endif 80 81 /* USB */ 82 #ifdef CONFIG_CMD_USB 83 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 84 #define CONFIG_SYS_USB_EHCI_CPU_INIT 85 #endif 86 87 /* Realtime clock */ 88 #define CONFIG_MCFRTC 89 #undef RTC_DEBUG 90 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 91 92 /* Timer */ 93 #define CONFIG_MCFTMR 94 #undef CONFIG_MCFPIT 95 96 /* I2c */ 97 #define CONFIG_SYS_I2C 98 #define CONFIG_SYS_I2C_FSL 99 #define CONFIG_SYS_FSL_I2C_SPEED 80000 100 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 101 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 102 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 103 104 /* DSPI and Serial Flash */ 105 #define CONFIG_CF_DSPI 106 #define CONFIG_HARD_SPI 107 #define CONFIG_SYS_SBFHDR_SIZE 0x7 108 #ifdef CONFIG_CMD_SPI 109 # define CONFIG_SYS_DSPI_CS2 110 111 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 112 DSPI_CTAR_PCSSCK_1CLK | \ 113 DSPI_CTAR_PASC(0) | \ 114 DSPI_CTAR_PDT(0) | \ 115 DSPI_CTAR_CSSCK(0) | \ 116 DSPI_CTAR_ASC(0) | \ 117 DSPI_CTAR_DT(1)) 118 #endif 119 120 /* Input, PCI, Flexbus, and VCO */ 121 #define CONFIG_EXTRA_CLOCK 122 123 #define CONFIG_SYS_INPUT_CLKSRC 16000000 124 125 #define CONFIG_PRAM 2048 /* 2048 KB */ 126 127 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 128 129 #define CONFIG_SYS_MBAR 0xFC000000 130 131 /* 132 * Low Level Configuration Settings 133 * (address mappings, register initial values, etc.) 134 * You should know what you are doing if you make changes here. 135 */ 136 137 /* 138 * Definitions for initial stack pointer and data area (in DPRAM) 139 */ 140 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 141 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 142 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 143 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 144 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 145 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 146 147 /* 148 * Start addresses for the final memory configuration 149 * (Set up by the startup code) 150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 151 */ 152 #define CONFIG_SYS_SDRAM_BASE 0x40000000 153 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 154 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 155 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 156 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 157 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 158 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 159 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 160 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 162 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 163 164 #ifdef CONFIG_CF_SBF 165 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 166 #else 167 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 168 #endif 169 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 170 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 171 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 172 173 /* Initial Memory map for Linux */ 174 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 175 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 176 177 /* 178 * Configuration for environment 179 * Environment is not embedded in u-boot. First time runing may have env 180 * crc error warning if there is no correct environment on the flash. 181 */ 182 #ifdef CONFIG_CF_SBF 183 # define CONFIG_ENV_SPI_CS 2 184 #endif 185 #define CONFIG_ENV_OVERWRITE 1 186 187 /*----------------------------------------------------------------------- 188 * FLASH organization 189 */ 190 #ifdef CONFIG_SYS_STMICRO_BOOT 191 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 192 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 193 # define CONFIG_ENV_OFFSET 0x30000 194 # define CONFIG_ENV_SIZE 0x1000 195 # define CONFIG_ENV_SECT_SIZE 0x10000 196 #endif 197 #ifdef CONFIG_SYS_SPANSION_BOOT 198 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 199 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 200 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 201 # define CONFIG_ENV_SIZE 0x1000 202 # define CONFIG_ENV_SECT_SIZE 0x8000 203 #endif 204 205 #define CONFIG_SYS_FLASH_CFI 206 #ifdef CONFIG_SYS_FLASH_CFI 207 # define CONFIG_FLASH_CFI_DRIVER 1 208 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 209 # define CONFIG_FLASH_SPANSION_S29WS_N 1 210 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 211 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 212 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 213 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 214 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 215 # define CONFIG_SYS_FLASH_CHECKSUM 216 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 217 #endif 218 219 #define LDS_BOARD_TEXT \ 220 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 221 arch/m68k/lib/built-in.o (.text*) 222 223 /* 224 * This is setting for JFFS2 support in u-boot. 225 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 226 */ 227 #ifdef CONFIG_CMD_JFFS2 228 # define CONFIG_JFFS2_DEV "nor0" 229 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 230 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 231 #endif 232 233 /*----------------------------------------------------------------------- 234 * Cache Configuration 235 */ 236 #define CONFIG_SYS_CACHELINE_SIZE 16 237 238 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 239 CONFIG_SYS_INIT_RAM_SIZE - 8) 240 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 241 CONFIG_SYS_INIT_RAM_SIZE - 4) 242 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 243 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 244 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 245 CF_ACR_EN | CF_ACR_SM_ALL) 246 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 247 CF_CACR_DISD | CF_CACR_INVI | \ 248 CF_CACR_CEIB | CF_CACR_DCM | \ 249 CF_CACR_EUSP) 250 251 /*----------------------------------------------------------------------- 252 * Memory bank definitions 253 */ 254 /* 255 * CS0 - NOR Flash 256 * CS1 - Available 257 * CS2 - Available 258 * CS3 - Available 259 * CS4 - Available 260 * CS5 - Available 261 */ 262 263 #ifdef CONFIG_CF_SBF 264 #define CONFIG_SYS_CS0_BASE 0x04000000 265 #define CONFIG_SYS_CS0_MASK 0x00FF0001 266 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 267 #else 268 #define CONFIG_SYS_CS0_BASE 0x00000000 269 #define CONFIG_SYS_CS0_MASK 0x00FF0001 270 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 271 #endif 272 273 #endif /* _M52277EVB_H */ 274