1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M52277EVB /* M52277EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #define CONFIG_CMD_CACHE 41 #define CONFIG_CMD_DATE 42 #define CONFIG_CMD_I2C 43 #define CONFIG_CMD_JFFS2 44 #define CONFIG_CMD_REGINFO 45 #undef CONFIG_CMD_USB 46 #undef CONFIG_CMD_BMP 47 #define CONFIG_CMD_SPI 48 #define CONFIG_CMD_SF 49 50 #define CONFIG_HOSTNAME M52277EVB 51 #define CONFIG_SYS_UBOOT_END 0x3FFFF 52 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 53 #ifdef CONFIG_SYS_STMICRO_BOOT 54 /* ST Micro serial flash */ 55 #define CONFIG_EXTRA_ENV_SETTINGS \ 56 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 57 "loadaddr=0x40010000\0" \ 58 "uboot=u-boot.bin\0" \ 59 "load=loadb ${loadaddr} ${baudrate};" \ 60 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 61 "upd=run load; run prog\0" \ 62 "prog=sf probe 0:2 10000 1;" \ 63 "sf erase 0 30000;" \ 64 "sf write ${loadaddr} 0 30000;" \ 65 "save\0" \ 66 "" 67 #endif 68 #ifdef CONFIG_SYS_SPANSION_BOOT 69 #define CONFIG_EXTRA_ENV_SETTINGS \ 70 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 71 "loadaddr=0x40010000\0" \ 72 "uboot=u-boot.bin\0" \ 73 "load=loadb ${loadaddr} ${baudrate}\0" \ 74 "upd=run load; run prog\0" \ 75 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 76 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 77 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 78 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 79 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 80 " ${filesize}; save\0" \ 81 "updsbf=run loadsbf; run progsbf\0" \ 82 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 83 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 84 "progsbf=sf probe 0:2 10000 1;" \ 85 "sf erase 0 30000;" \ 86 "sf write ${loadaddr} 0 30000;" \ 87 "" 88 #endif 89 90 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 91 /* LCD */ 92 #ifdef CONFIG_CMD_BMP 93 #define CONFIG_LCD 94 #define CONFIG_SPLASH_SCREEN 95 #define CONFIG_LCD_LOGO 96 #define CONFIG_SHARP_LQ035Q7DH06 97 #endif 98 99 /* USB */ 100 #ifdef CONFIG_CMD_USB 101 #define CONFIG_USB_EHCI 102 #define CONFIG_USB_STORAGE 103 #define CONFIG_DOS_PARTITION 104 #define CONFIG_MAC_PARTITION 105 #define CONFIG_ISO_PARTITION 106 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 107 #define CONFIG_SYS_USB_EHCI_CPU_INIT 108 #endif 109 110 /* Realtime clock */ 111 #define CONFIG_MCFRTC 112 #undef RTC_DEBUG 113 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 114 115 /* Timer */ 116 #define CONFIG_MCFTMR 117 #undef CONFIG_MCFPIT 118 119 /* I2c */ 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_I2C_FSL 122 #define CONFIG_SYS_FSL_I2C_SPEED 80000 123 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 124 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 125 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 126 127 /* DSPI and Serial Flash */ 128 #define CONFIG_CF_SPI 129 #define CONFIG_CF_DSPI 130 #define CONFIG_HARD_SPI 131 #define CONFIG_SYS_SBFHDR_SIZE 0x7 132 #ifdef CONFIG_CMD_SPI 133 # define CONFIG_SYS_DSPI_CS2 134 # define CONFIG_SPI_FLASH_STMICRO 135 136 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 137 DSPI_CTAR_PCSSCK_1CLK | \ 138 DSPI_CTAR_PASC(0) | \ 139 DSPI_CTAR_PDT(0) | \ 140 DSPI_CTAR_CSSCK(0) | \ 141 DSPI_CTAR_ASC(0) | \ 142 DSPI_CTAR_DT(1)) 143 #endif 144 145 /* Input, PCI, Flexbus, and VCO */ 146 #define CONFIG_EXTRA_CLOCK 147 148 #define CONFIG_SYS_INPUT_CLKSRC 16000000 149 150 #define CONFIG_PRAM 2048 /* 2048 KB */ 151 152 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 153 154 #if defined(CONFIG_CMD_KGDB) 155 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 156 #else 157 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 158 #endif 159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 160 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 161 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 162 163 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 164 165 #define CONFIG_SYS_MBAR 0xFC000000 166 167 /* 168 * Low Level Configuration Settings 169 * (address mappings, register initial values, etc.) 170 * You should know what you are doing if you make changes here. 171 */ 172 173 /* 174 * Definitions for initial stack pointer and data area (in DPRAM) 175 */ 176 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 177 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 178 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 179 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 180 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 181 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 182 183 /* 184 * Start addresses for the final memory configuration 185 * (Set up by the startup code) 186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 187 */ 188 #define CONFIG_SYS_SDRAM_BASE 0x40000000 189 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 190 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 191 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 192 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 193 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 194 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 195 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 196 197 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 198 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 199 200 #ifdef CONFIG_CF_SBF 201 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 202 #else 203 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 204 #endif 205 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 206 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 207 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 208 209 /* Initial Memory map for Linux */ 210 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 211 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 212 213 /* 214 * Configuration for environment 215 * Environment is not embedded in u-boot. First time runing may have env 216 * crc error warning if there is no correct environment on the flash. 217 */ 218 #ifdef CONFIG_CF_SBF 219 # define CONFIG_ENV_IS_IN_SPI_FLASH 220 # define CONFIG_ENV_SPI_CS 2 221 #else 222 # define CONFIG_ENV_IS_IN_FLASH 1 223 #endif 224 #define CONFIG_ENV_OVERWRITE 1 225 226 /*----------------------------------------------------------------------- 227 * FLASH organization 228 */ 229 #ifdef CONFIG_SYS_STMICRO_BOOT 230 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 231 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 232 # define CONFIG_ENV_OFFSET 0x30000 233 # define CONFIG_ENV_SIZE 0x1000 234 # define CONFIG_ENV_SECT_SIZE 0x10000 235 #endif 236 #ifdef CONFIG_SYS_SPANSION_BOOT 237 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 238 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 239 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 240 # define CONFIG_ENV_SIZE 0x1000 241 # define CONFIG_ENV_SECT_SIZE 0x8000 242 #endif 243 244 #define CONFIG_SYS_FLASH_CFI 245 #ifdef CONFIG_SYS_FLASH_CFI 246 # define CONFIG_FLASH_CFI_DRIVER 1 247 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 248 # define CONFIG_FLASH_SPANSION_S29WS_N 1 249 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 250 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 251 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 252 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 253 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 254 # define CONFIG_SYS_FLASH_CHECKSUM 255 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 256 #endif 257 258 #define LDS_BOARD_TEXT \ 259 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 260 arch/m68k/lib/built-in.o (.text*) 261 262 /* 263 * This is setting for JFFS2 support in u-boot. 264 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 265 */ 266 #ifdef CONFIG_CMD_JFFS2 267 # define CONFIG_JFFS2_DEV "nor0" 268 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 269 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 270 #endif 271 272 /*----------------------------------------------------------------------- 273 * Cache Configuration 274 */ 275 #define CONFIG_SYS_CACHELINE_SIZE 16 276 277 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 278 CONFIG_SYS_INIT_RAM_SIZE - 8) 279 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 280 CONFIG_SYS_INIT_RAM_SIZE - 4) 281 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 282 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 283 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 284 CF_ACR_EN | CF_ACR_SM_ALL) 285 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 286 CF_CACR_DISD | CF_CACR_INVI | \ 287 CF_CACR_CEIB | CF_CACR_DCM | \ 288 CF_CACR_EUSP) 289 290 /*----------------------------------------------------------------------- 291 * Memory bank definitions 292 */ 293 /* 294 * CS0 - NOR Flash 295 * CS1 - Available 296 * CS2 - Available 297 * CS3 - Available 298 * CS4 - Available 299 * CS5 - Available 300 */ 301 302 #ifdef CONFIG_CF_SBF 303 #define CONFIG_SYS_CS0_BASE 0x04000000 304 #define CONFIG_SYS_CS0_MASK 0x00FF0001 305 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 306 #else 307 #define CONFIG_SYS_CS0_BASE 0x00000000 308 #define CONFIG_SYS_CS0_MASK 0x00FF0001 309 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 310 #endif 311 312 #endif /* _M52277EVB_H */ 313