1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M52277EVB /* M52277EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #include <config_cmd_default.h> 41 42 #define CONFIG_CMD_CACHE 43 #define CONFIG_CMD_DATE 44 #define CONFIG_CMD_ELF 45 #define CONFIG_CMD_FLASH 46 #define CONFIG_CMD_I2C 47 #define CONFIG_CMD_JFFS2 48 #define CONFIG_CMD_LOADB 49 #define CONFIG_CMD_LOADS 50 #define CONFIG_CMD_MEMORY 51 #define CONFIG_CMD_MISC 52 #undef CONFIG_CMD_NFS 53 #define CONFIG_CMD_REGINFO 54 #undef CONFIG_CMD_USB 55 #undef CONFIG_CMD_BMP 56 #define CONFIG_CMD_SPI 57 #define CONFIG_CMD_SF 58 59 #define CONFIG_HOSTNAME M52277EVB 60 #define CONFIG_SYS_UBOOT_END 0x3FFFF 61 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 62 #ifdef CONFIG_SYS_STMICRO_BOOT 63 /* ST Micro serial flash */ 64 #define CONFIG_EXTRA_ENV_SETTINGS \ 65 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 66 "loadaddr=0x40010000\0" \ 67 "uboot=u-boot.bin\0" \ 68 "load=loadb ${loadaddr} ${baudrate};" \ 69 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 70 "upd=run load; run prog\0" \ 71 "prog=sf probe 0:2 10000 1;" \ 72 "sf erase 0 30000;" \ 73 "sf write ${loadaddr} 0 30000;" \ 74 "save\0" \ 75 "" 76 #endif 77 #ifdef CONFIG_SYS_SPANSION_BOOT 78 #define CONFIG_EXTRA_ENV_SETTINGS \ 79 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 80 "loadaddr=0x40010000\0" \ 81 "uboot=u-boot.bin\0" \ 82 "load=loadb ${loadaddr} ${baudrate}\0" \ 83 "upd=run load; run prog\0" \ 84 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 85 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 86 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 87 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 88 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 89 " ${filesize}; save\0" \ 90 "updsbf=run loadsbf; run progsbf\0" \ 91 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 92 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 93 "progsbf=sf probe 0:2 10000 1;" \ 94 "sf erase 0 30000;" \ 95 "sf write ${loadaddr} 0 30000;" \ 96 "" 97 #endif 98 99 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 100 /* LCD */ 101 #ifdef CONFIG_CMD_BMP 102 #define CONFIG_LCD 103 #define CONFIG_SPLASH_SCREEN 104 #define CONFIG_LCD_LOGO 105 #define CONFIG_SHARP_LQ035Q7DH06 106 #endif 107 108 /* USB */ 109 #ifdef CONFIG_CMD_USB 110 #define CONFIG_USB_EHCI 111 #define CONFIG_USB_STORAGE 112 #define CONFIG_DOS_PARTITION 113 #define CONFIG_MAC_PARTITION 114 #define CONFIG_ISO_PARTITION 115 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 116 #define CONFIG_SYS_USB_EHCI_CPU_INIT 117 #endif 118 119 /* Realtime clock */ 120 #define CONFIG_MCFRTC 121 #undef RTC_DEBUG 122 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 123 124 /* Timer */ 125 #define CONFIG_MCFTMR 126 #undef CONFIG_MCFPIT 127 128 /* I2c */ 129 #define CONFIG_SYS_I2C 130 #define CONFIG_SYS_I2C_FSL 131 #define CONFIG_SYS_FSL_I2C_SPEED 80000 132 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 133 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 134 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 135 136 /* DSPI and Serial Flash */ 137 #define CONFIG_CF_SPI 138 #define CONFIG_CF_DSPI 139 #define CONFIG_HARD_SPI 140 #define CONFIG_SYS_SBFHDR_SIZE 0x7 141 #ifdef CONFIG_CMD_SPI 142 # define CONFIG_SYS_DSPI_CS2 143 # define CONFIG_SPI_FLASH 144 # define CONFIG_SPI_FLASH_STMICRO 145 146 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 147 DSPI_CTAR_PCSSCK_1CLK | \ 148 DSPI_CTAR_PASC(0) | \ 149 DSPI_CTAR_PDT(0) | \ 150 DSPI_CTAR_CSSCK(0) | \ 151 DSPI_CTAR_ASC(0) | \ 152 DSPI_CTAR_DT(1)) 153 #endif 154 155 /* Input, PCI, Flexbus, and VCO */ 156 #define CONFIG_EXTRA_CLOCK 157 158 #define CONFIG_SYS_INPUT_CLKSRC 16000000 159 160 #define CONFIG_PRAM 2048 /* 2048 KB */ 161 162 #define CONFIG_SYS_PROMPT "-> " 163 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 164 165 #if defined(CONFIG_CMD_KGDB) 166 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 167 #else 168 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 169 #endif 170 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 171 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 172 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 173 174 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 175 176 #define CONFIG_SYS_MBAR 0xFC000000 177 178 /* 179 * Low Level Configuration Settings 180 * (address mappings, register initial values, etc.) 181 * You should know what you are doing if you make changes here. 182 */ 183 184 /* 185 * Definitions for initial stack pointer and data area (in DPRAM) 186 */ 187 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 188 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 189 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 190 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 191 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 192 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 193 194 /* 195 * Start addresses for the final memory configuration 196 * (Set up by the startup code) 197 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 198 */ 199 #define CONFIG_SYS_SDRAM_BASE 0x40000000 200 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 201 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 202 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 203 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 204 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 205 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 206 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 207 208 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 209 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 210 211 #ifdef CONFIG_CF_SBF 212 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 213 #else 214 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 215 #endif 216 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 217 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 218 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 219 220 /* Initial Memory map for Linux */ 221 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 222 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 223 224 /* 225 * Configuration for environment 226 * Environment is not embedded in u-boot. First time runing may have env 227 * crc error warning if there is no correct environment on the flash. 228 */ 229 #ifdef CONFIG_CF_SBF 230 # define CONFIG_ENV_IS_IN_SPI_FLASH 231 # define CONFIG_ENV_SPI_CS 2 232 #else 233 # define CONFIG_ENV_IS_IN_FLASH 1 234 #endif 235 #define CONFIG_ENV_OVERWRITE 1 236 237 /*----------------------------------------------------------------------- 238 * FLASH organization 239 */ 240 #ifdef CONFIG_SYS_STMICRO_BOOT 241 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 242 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 243 # define CONFIG_ENV_OFFSET 0x30000 244 # define CONFIG_ENV_SIZE 0x1000 245 # define CONFIG_ENV_SECT_SIZE 0x10000 246 #endif 247 #ifdef CONFIG_SYS_SPANSION_BOOT 248 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 249 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 250 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 251 # define CONFIG_ENV_SIZE 0x1000 252 # define CONFIG_ENV_SECT_SIZE 0x8000 253 #endif 254 255 #define CONFIG_SYS_FLASH_CFI 256 #ifdef CONFIG_SYS_FLASH_CFI 257 # define CONFIG_FLASH_CFI_DRIVER 1 258 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 259 # define CONFIG_FLASH_SPANSION_S29WS_N 1 260 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 261 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 262 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 263 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 264 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 265 # define CONFIG_SYS_FLASH_CHECKSUM 266 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 267 #endif 268 269 #define LDS_BOARD_TEXT \ 270 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 271 arch/m68k/lib/built-in.o (.text*) 272 273 /* 274 * This is setting for JFFS2 support in u-boot. 275 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 276 */ 277 #ifdef CONFIG_CMD_JFFS2 278 # define CONFIG_JFFS2_DEV "nor0" 279 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 280 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 281 #endif 282 283 /*----------------------------------------------------------------------- 284 * Cache Configuration 285 */ 286 #define CONFIG_SYS_CACHELINE_SIZE 16 287 288 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 289 CONFIG_SYS_INIT_RAM_SIZE - 8) 290 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 291 CONFIG_SYS_INIT_RAM_SIZE - 4) 292 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 293 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 294 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 295 CF_ACR_EN | CF_ACR_SM_ALL) 296 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 297 CF_CACR_DISD | CF_CACR_INVI | \ 298 CF_CACR_CEIB | CF_CACR_DCM | \ 299 CF_CACR_EUSP) 300 301 /*----------------------------------------------------------------------- 302 * Memory bank definitions 303 */ 304 /* 305 * CS0 - NOR Flash 306 * CS1 - Available 307 * CS2 - Available 308 * CS3 - Available 309 * CS4 - Available 310 * CS5 - Available 311 */ 312 313 #ifdef CONFIG_CF_SBF 314 #define CONFIG_SYS_CS0_BASE 0x04000000 315 #define CONFIG_SYS_CS0_MASK 0x00FF0001 316 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 317 #else 318 #define CONFIG_SYS_CS0_BASE 0x00000000 319 #define CONFIG_SYS_CS0_MASK 0x00FF0001 320 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 321 #endif 322 323 #endif /* _M52277EVB_H */ 324