1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M52277EVB /* M52277EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #define CONFIG_CMD_CACHE 41 #define CONFIG_CMD_DATE 42 #define CONFIG_CMD_ELF 43 #define CONFIG_CMD_I2C 44 #define CONFIG_CMD_JFFS2 45 #define CONFIG_CMD_REGINFO 46 #undef CONFIG_CMD_USB 47 #undef CONFIG_CMD_BMP 48 #define CONFIG_CMD_SPI 49 #define CONFIG_CMD_SF 50 51 #define CONFIG_HOSTNAME M52277EVB 52 #define CONFIG_SYS_UBOOT_END 0x3FFFF 53 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 54 #ifdef CONFIG_SYS_STMICRO_BOOT 55 /* ST Micro serial flash */ 56 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 58 "loadaddr=0x40010000\0" \ 59 "uboot=u-boot.bin\0" \ 60 "load=loadb ${loadaddr} ${baudrate};" \ 61 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 62 "upd=run load; run prog\0" \ 63 "prog=sf probe 0:2 10000 1;" \ 64 "sf erase 0 30000;" \ 65 "sf write ${loadaddr} 0 30000;" \ 66 "save\0" \ 67 "" 68 #endif 69 #ifdef CONFIG_SYS_SPANSION_BOOT 70 #define CONFIG_EXTRA_ENV_SETTINGS \ 71 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 72 "loadaddr=0x40010000\0" \ 73 "uboot=u-boot.bin\0" \ 74 "load=loadb ${loadaddr} ${baudrate}\0" \ 75 "upd=run load; run prog\0" \ 76 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 77 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 78 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 79 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 80 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 81 " ${filesize}; save\0" \ 82 "updsbf=run loadsbf; run progsbf\0" \ 83 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 84 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 85 "progsbf=sf probe 0:2 10000 1;" \ 86 "sf erase 0 30000;" \ 87 "sf write ${loadaddr} 0 30000;" \ 88 "" 89 #endif 90 91 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 92 /* LCD */ 93 #ifdef CONFIG_CMD_BMP 94 #define CONFIG_LCD 95 #define CONFIG_SPLASH_SCREEN 96 #define CONFIG_LCD_LOGO 97 #define CONFIG_SHARP_LQ035Q7DH06 98 #endif 99 100 /* USB */ 101 #ifdef CONFIG_CMD_USB 102 #define CONFIG_USB_EHCI 103 #define CONFIG_USB_STORAGE 104 #define CONFIG_DOS_PARTITION 105 #define CONFIG_MAC_PARTITION 106 #define CONFIG_ISO_PARTITION 107 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 108 #define CONFIG_SYS_USB_EHCI_CPU_INIT 109 #endif 110 111 /* Realtime clock */ 112 #define CONFIG_MCFRTC 113 #undef RTC_DEBUG 114 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 115 116 /* Timer */ 117 #define CONFIG_MCFTMR 118 #undef CONFIG_MCFPIT 119 120 /* I2c */ 121 #define CONFIG_SYS_I2C 122 #define CONFIG_SYS_I2C_FSL 123 #define CONFIG_SYS_FSL_I2C_SPEED 80000 124 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 125 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 126 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 127 128 /* DSPI and Serial Flash */ 129 #define CONFIG_CF_SPI 130 #define CONFIG_CF_DSPI 131 #define CONFIG_HARD_SPI 132 #define CONFIG_SYS_SBFHDR_SIZE 0x7 133 #ifdef CONFIG_CMD_SPI 134 # define CONFIG_SYS_DSPI_CS2 135 # define CONFIG_SPI_FLASH_STMICRO 136 137 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 138 DSPI_CTAR_PCSSCK_1CLK | \ 139 DSPI_CTAR_PASC(0) | \ 140 DSPI_CTAR_PDT(0) | \ 141 DSPI_CTAR_CSSCK(0) | \ 142 DSPI_CTAR_ASC(0) | \ 143 DSPI_CTAR_DT(1)) 144 #endif 145 146 /* Input, PCI, Flexbus, and VCO */ 147 #define CONFIG_EXTRA_CLOCK 148 149 #define CONFIG_SYS_INPUT_CLKSRC 16000000 150 151 #define CONFIG_PRAM 2048 /* 2048 KB */ 152 153 #define CONFIG_SYS_PROMPT "-> " 154 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 155 156 #if defined(CONFIG_CMD_KGDB) 157 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 158 #else 159 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 160 #endif 161 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 162 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 163 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 164 165 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 166 167 #define CONFIG_SYS_MBAR 0xFC000000 168 169 /* 170 * Low Level Configuration Settings 171 * (address mappings, register initial values, etc.) 172 * You should know what you are doing if you make changes here. 173 */ 174 175 /* 176 * Definitions for initial stack pointer and data area (in DPRAM) 177 */ 178 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 180 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 181 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 182 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 183 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 184 185 /* 186 * Start addresses for the final memory configuration 187 * (Set up by the startup code) 188 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 189 */ 190 #define CONFIG_SYS_SDRAM_BASE 0x40000000 191 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 192 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 193 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 194 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 195 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 196 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 197 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 198 199 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 200 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 201 202 #ifdef CONFIG_CF_SBF 203 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 204 #else 205 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 206 #endif 207 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 208 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 209 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 210 211 /* Initial Memory map for Linux */ 212 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 213 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 214 215 /* 216 * Configuration for environment 217 * Environment is not embedded in u-boot. First time runing may have env 218 * crc error warning if there is no correct environment on the flash. 219 */ 220 #ifdef CONFIG_CF_SBF 221 # define CONFIG_ENV_IS_IN_SPI_FLASH 222 # define CONFIG_ENV_SPI_CS 2 223 #else 224 # define CONFIG_ENV_IS_IN_FLASH 1 225 #endif 226 #define CONFIG_ENV_OVERWRITE 1 227 228 /*----------------------------------------------------------------------- 229 * FLASH organization 230 */ 231 #ifdef CONFIG_SYS_STMICRO_BOOT 232 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 233 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 234 # define CONFIG_ENV_OFFSET 0x30000 235 # define CONFIG_ENV_SIZE 0x1000 236 # define CONFIG_ENV_SECT_SIZE 0x10000 237 #endif 238 #ifdef CONFIG_SYS_SPANSION_BOOT 239 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 240 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 241 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 242 # define CONFIG_ENV_SIZE 0x1000 243 # define CONFIG_ENV_SECT_SIZE 0x8000 244 #endif 245 246 #define CONFIG_SYS_FLASH_CFI 247 #ifdef CONFIG_SYS_FLASH_CFI 248 # define CONFIG_FLASH_CFI_DRIVER 1 249 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 250 # define CONFIG_FLASH_SPANSION_S29WS_N 1 251 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 252 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 253 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 254 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 255 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 256 # define CONFIG_SYS_FLASH_CHECKSUM 257 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 258 #endif 259 260 #define LDS_BOARD_TEXT \ 261 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 262 arch/m68k/lib/built-in.o (.text*) 263 264 /* 265 * This is setting for JFFS2 support in u-boot. 266 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 267 */ 268 #ifdef CONFIG_CMD_JFFS2 269 # define CONFIG_JFFS2_DEV "nor0" 270 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 271 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 272 #endif 273 274 /*----------------------------------------------------------------------- 275 * Cache Configuration 276 */ 277 #define CONFIG_SYS_CACHELINE_SIZE 16 278 279 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 280 CONFIG_SYS_INIT_RAM_SIZE - 8) 281 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 282 CONFIG_SYS_INIT_RAM_SIZE - 4) 283 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 284 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 285 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 286 CF_ACR_EN | CF_ACR_SM_ALL) 287 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 288 CF_CACR_DISD | CF_CACR_INVI | \ 289 CF_CACR_CEIB | CF_CACR_DCM | \ 290 CF_CACR_EUSP) 291 292 /*----------------------------------------------------------------------- 293 * Memory bank definitions 294 */ 295 /* 296 * CS0 - NOR Flash 297 * CS1 - Available 298 * CS2 - Available 299 * CS3 - Available 300 * CS4 - Available 301 * CS5 - Available 302 */ 303 304 #ifdef CONFIG_CF_SBF 305 #define CONFIG_SYS_CS0_BASE 0x04000000 306 #define CONFIG_SYS_CS0_MASK 0x00FF0001 307 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 308 #else 309 #define CONFIG_SYS_CS0_BASE 0x00000000 310 #define CONFIG_SYS_CS0_MASK 0x00FF0001 311 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 312 #endif 313 314 #endif /* _M52277EVB_H */ 315