1 /* 2 * Configuation settings for the Freescale MCF5208EVBe. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _M5208EVBE_H 11 #define _M5208EVBE_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_MCFUART 18 #define CONFIG_SYS_UART_PORT (0) 19 #define CONFIG_BAUDRATE 115200 20 21 #undef CONFIG_WATCHDOG 22 #define CONFIG_WATCHDOG_TIMEOUT 5000 23 24 /* Command line configuration */ 25 #include <config_cmd_default.h> 26 27 #define CONFIG_CMD_CACHE 28 #define CONFIG_CMD_ELF 29 #define CONFIG_CMD_FLASH 30 #undef CONFIG_CMD_I2C 31 #define CONFIG_CMD_MEMORY 32 #define CONFIG_CMD_MISC 33 #define CONFIG_CMD_MII 34 #define CONFIG_CMD_NET 35 #define CONFIG_CMD_PING 36 #define CONFIG_CMD_REGINFO 37 38 #define CONFIG_MCFFEC 39 #ifdef CONFIG_MCFFEC 40 # define CONFIG_MII 1 41 # define CONFIG_MII_INIT 1 42 # define CONFIG_SYS_DISCOVER_PHY 43 # define CONFIG_SYS_RX_ETH_BUFFER 8 44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 # define CONFIG_HAS_ETH1 46 47 # define CONFIG_SYS_FEC0_PINMUX 0 48 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 49 # define MCFFEC_TOUT_LOOP 50000 50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 51 # ifndef CONFIG_SYS_DISCOVER_PHY 52 # define FECDUPLEX FULL 53 # define FECSPEED _100BASET 54 # else 55 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 # endif 58 # endif /* CONFIG_SYS_DISCOVER_PHY */ 59 #endif 60 61 /* Timer */ 62 #define CONFIG_MCFTMR 63 #undef CONFIG_MCFPIT 64 65 /* I2C */ 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_I2C_FSL 68 #define CONFIG_SYS_FSL_I2C_SPEED 80000 69 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 70 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 71 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 72 73 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 74 #define CONFIG_UDP_CHECKSUM 75 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 78 # define CONFIG_IPADDR 192.162.1.2 79 # define CONFIG_NETMASK 255.255.255.0 80 # define CONFIG_SERVERIP 192.162.1.1 81 # define CONFIG_GATEWAYIP 192.162.1.1 82 # define CONFIG_OVERWRITE_ETHADDR_ONCE 83 #endif /* CONFIG_MCFFEC */ 84 85 #define CONFIG_HOSTNAME M5208EVBe 86 #define CONFIG_EXTRA_ENV_SETTINGS \ 87 "netdev=eth0\0" \ 88 "loadaddr=40010000\0" \ 89 "u-boot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr) ${u-boot}\0" \ 91 "upd=run load; run prog\0" \ 92 "prog=prot off 0 3ffff;" \ 93 "era 0 3ffff;" \ 94 "cp.b ${loadaddr} 0 ${filesize};" \ 95 "save\0" \ 96 "" 97 98 #define CONFIG_PRAM 512 /* 512 KB */ 99 #define CONFIG_SYS_PROMPT "-> " 100 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 101 102 #ifdef CONFIG_CMD_KGDB 103 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 104 #else 105 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 #endif 107 108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 109 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 111 #define CONFIG_SYS_LOAD_ADDR 0x40010000 112 113 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 114 #define CONFIG_SYS_PLL_ODR 0x36 115 #define CONFIG_SYS_PLL_FDR 0x7D 116 117 #define CONFIG_SYS_MBAR 0xFC000000 118 119 /* 120 * Low Level Configuration Settings 121 * (address mappings, register initial values, etc.) 122 * You should know what you are doing if you make changes here. 123 */ 124 /* Definitions for initial stack pointer and data area (in DPRAM) */ 125 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 126 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 127 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 128 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 129 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 130 131 /* 132 * Start addresses for the final memory configuration 133 * (Set up by the startup code) 134 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 135 */ 136 #define CONFIG_SYS_SDRAM_BASE 0x40000000 137 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 138 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 139 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 140 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 141 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 142 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 143 144 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 145 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 146 147 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 148 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 149 150 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 151 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 152 153 /* 154 * For booting Linux, the board info and command line data 155 * have to be in the first 8 MB of memory, since this is 156 * the maximum mapped by the Linux kernel during initialization ?? 157 */ 158 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 159 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 160 161 /* FLASH organization */ 162 #define CONFIG_SYS_FLASH_CFI 163 #ifdef CONFIG_SYS_FLASH_CFI 164 # define CONFIG_FLASH_CFI_DRIVER 1 165 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 166 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 167 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 168 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 169 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 170 #endif 171 172 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 173 174 /* 175 * Configuration for environment 176 * Environment is embedded in u-boot in the second sector of the flash 177 */ 178 #define CONFIG_ENV_OFFSET 0x2000 179 #define CONFIG_ENV_SIZE 0x1000 180 #define CONFIG_ENV_SECT_SIZE 0x2000 181 #define CONFIG_ENV_IS_IN_FLASH 1 182 183 /* Cache Configuration */ 184 #define CONFIG_SYS_CACHELINE_SIZE 16 185 186 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 187 CONFIG_SYS_INIT_RAM_SIZE - 8) 188 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 189 CONFIG_SYS_INIT_RAM_SIZE - 4) 190 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 191 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 192 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 193 CF_ACR_EN | CF_ACR_SM_ALL) 194 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 195 CF_CACR_DISD | CF_CACR_INVI | \ 196 CF_CACR_CEIB | CF_CACR_DCM | \ 197 CF_CACR_EUSP) 198 199 /* Chipselect bank definitions */ 200 /* 201 * CS0 - NOR Flash 202 * CS1 - Available 203 * CS2 - Available 204 * CS3 - Available 205 * CS4 - Available 206 * CS5 - Available 207 */ 208 #define CONFIG_SYS_CS0_BASE 0 209 #define CONFIG_SYS_CS0_MASK 0x007F0001 210 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 211 212 #endif /* _M5208EVBE_H */ 213