1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5208EVBe. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef _M5208EVBE_H 10 #define _M5208EVBE_H 11 12 /* 13 * High Level Configuration Options 14 * (easy to change) 15 */ 16 #define CONFIG_MCFUART 17 #define CONFIG_SYS_UART_PORT (0) 18 19 #undef CONFIG_WATCHDOG 20 #define CONFIG_WATCHDOG_TIMEOUT 5000 21 22 #define CONFIG_MCFFEC 23 #ifdef CONFIG_MCFFEC 24 # define CONFIG_MII_INIT 1 25 # define CONFIG_SYS_DISCOVER_PHY 26 # define CONFIG_SYS_RX_ETH_BUFFER 8 27 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 28 # define CONFIG_HAS_ETH1 29 30 # define CONFIG_SYS_FEC0_PINMUX 0 31 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 32 # define MCFFEC_TOUT_LOOP 50000 33 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 34 # ifndef CONFIG_SYS_DISCOVER_PHY 35 # define FECDUPLEX FULL 36 # define FECSPEED _100BASET 37 # else 38 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 40 # endif 41 # endif /* CONFIG_SYS_DISCOVER_PHY */ 42 #endif 43 44 /* Timer */ 45 #define CONFIG_MCFTMR 46 #undef CONFIG_MCFPIT 47 48 /* I2C */ 49 #define CONFIG_SYS_I2C 50 #define CONFIG_SYS_I2C_FSL 51 #define CONFIG_SYS_FSL_I2C_SPEED 80000 52 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 53 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 54 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 55 56 #define CONFIG_UDP_CHECKSUM 57 58 #ifdef CONFIG_MCFFEC 59 # define CONFIG_IPADDR 192.162.1.2 60 # define CONFIG_NETMASK 255.255.255.0 61 # define CONFIG_SERVERIP 192.162.1.1 62 # define CONFIG_GATEWAYIP 192.162.1.1 63 #endif /* CONFIG_MCFFEC */ 64 65 #define CONFIG_HOSTNAME "M5208EVBe" 66 #define CONFIG_EXTRA_ENV_SETTINGS \ 67 "netdev=eth0\0" \ 68 "loadaddr=40010000\0" \ 69 "u-boot=u-boot.bin\0" \ 70 "load=tftp ${loadaddr) ${u-boot}\0" \ 71 "upd=run load; run prog\0" \ 72 "prog=prot off 0 3ffff;" \ 73 "era 0 3ffff;" \ 74 "cp.b ${loadaddr} 0 ${filesize};" \ 75 "save\0" \ 76 "" 77 78 #define CONFIG_PRAM 512 /* 512 KB */ 79 80 #define CONFIG_SYS_LOAD_ADDR 0x40010000 81 82 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 83 #define CONFIG_SYS_PLL_ODR 0x36 84 #define CONFIG_SYS_PLL_FDR 0x7D 85 86 #define CONFIG_SYS_MBAR 0xFC000000 87 88 /* 89 * Low Level Configuration Settings 90 * (address mappings, register initial values, etc.) 91 * You should know what you are doing if you make changes here. 92 */ 93 /* Definitions for initial stack pointer and data area (in DPRAM) */ 94 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 95 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 96 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 97 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 98 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 99 100 /* 101 * Start addresses for the final memory configuration 102 * (Set up by the startup code) 103 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 104 */ 105 #define CONFIG_SYS_SDRAM_BASE 0x40000000 106 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 107 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 108 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 109 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 110 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 111 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 112 113 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 114 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 115 116 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 117 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 118 119 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 120 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 121 122 /* 123 * For booting Linux, the board info and command line data 124 * have to be in the first 8 MB of memory, since this is 125 * the maximum mapped by the Linux kernel during initialization ?? 126 */ 127 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 128 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 129 130 /* FLASH organization */ 131 #ifdef CONFIG_SYS_FLASH_CFI 132 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 133 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 134 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 135 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 136 #endif 137 138 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 139 140 /* 141 * Configuration for environment 142 * Environment is embedded in u-boot in the second sector of the flash 143 */ 144 #define CONFIG_ENV_OFFSET 0x2000 145 #define CONFIG_ENV_SIZE 0x1000 146 #define CONFIG_ENV_SECT_SIZE 0x2000 147 148 #define LDS_BOARD_TEXT \ 149 . = DEFINED(env_offset) ? env_offset : .; \ 150 env/embedded.o(.text*); 151 152 /* Cache Configuration */ 153 #define CONFIG_SYS_CACHELINE_SIZE 16 154 155 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 156 CONFIG_SYS_INIT_RAM_SIZE - 8) 157 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 158 CONFIG_SYS_INIT_RAM_SIZE - 4) 159 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 160 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 161 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 162 CF_ACR_EN | CF_ACR_SM_ALL) 163 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 164 CF_CACR_DISD | CF_CACR_INVI | \ 165 CF_CACR_CEIB | CF_CACR_DCM | \ 166 CF_CACR_EUSP) 167 168 /* Chipselect bank definitions */ 169 /* 170 * CS0 - NOR Flash 171 * CS1 - Available 172 * CS2 - Available 173 * CS3 - Available 174 * CS4 - Available 175 * CS5 - Available 176 */ 177 #define CONFIG_SYS_CS0_BASE 0 178 #define CONFIG_SYS_CS0_MASK 0x007F0001 179 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 180 181 #endif /* _M5208EVBE_H */ 182