1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5208EVBe. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef _M5208EVBE_H 10 #define _M5208EVBE_H 11 12 /* 13 * High Level Configuration Options 14 * (easy to change) 15 */ 16 #define CONFIG_MCFUART 17 #define CONFIG_SYS_UART_PORT (0) 18 19 #undef CONFIG_WATCHDOG 20 #define CONFIG_WATCHDOG_TIMEOUT 5000 21 22 #define CONFIG_MCFFEC 23 #ifdef CONFIG_MCFFEC 24 # define CONFIG_MII 1 25 # define CONFIG_MII_INIT 1 26 # define CONFIG_SYS_DISCOVER_PHY 27 # define CONFIG_SYS_RX_ETH_BUFFER 8 28 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 29 # define CONFIG_HAS_ETH1 30 31 # define CONFIG_SYS_FEC0_PINMUX 0 32 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 33 # define MCFFEC_TOUT_LOOP 50000 34 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 35 # ifndef CONFIG_SYS_DISCOVER_PHY 36 # define FECDUPLEX FULL 37 # define FECSPEED _100BASET 38 # else 39 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 # endif 42 # endif /* CONFIG_SYS_DISCOVER_PHY */ 43 #endif 44 45 /* Timer */ 46 #define CONFIG_MCFTMR 47 #undef CONFIG_MCFPIT 48 49 /* I2C */ 50 #define CONFIG_SYS_I2C 51 #define CONFIG_SYS_I2C_FSL 52 #define CONFIG_SYS_FSL_I2C_SPEED 80000 53 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 54 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 55 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 56 57 #define CONFIG_UDP_CHECKSUM 58 59 #ifdef CONFIG_MCFFEC 60 # define CONFIG_IPADDR 192.162.1.2 61 # define CONFIG_NETMASK 255.255.255.0 62 # define CONFIG_SERVERIP 192.162.1.1 63 # define CONFIG_GATEWAYIP 192.162.1.1 64 #endif /* CONFIG_MCFFEC */ 65 66 #define CONFIG_HOSTNAME "M5208EVBe" 67 #define CONFIG_EXTRA_ENV_SETTINGS \ 68 "netdev=eth0\0" \ 69 "loadaddr=40010000\0" \ 70 "u-boot=u-boot.bin\0" \ 71 "load=tftp ${loadaddr) ${u-boot}\0" \ 72 "upd=run load; run prog\0" \ 73 "prog=prot off 0 3ffff;" \ 74 "era 0 3ffff;" \ 75 "cp.b ${loadaddr} 0 ${filesize};" \ 76 "save\0" \ 77 "" 78 79 #define CONFIG_PRAM 512 /* 512 KB */ 80 81 #define CONFIG_SYS_LOAD_ADDR 0x40010000 82 83 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 84 #define CONFIG_SYS_PLL_ODR 0x36 85 #define CONFIG_SYS_PLL_FDR 0x7D 86 87 #define CONFIG_SYS_MBAR 0xFC000000 88 89 /* 90 * Low Level Configuration Settings 91 * (address mappings, register initial values, etc.) 92 * You should know what you are doing if you make changes here. 93 */ 94 /* Definitions for initial stack pointer and data area (in DPRAM) */ 95 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 96 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 97 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 98 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 99 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 100 101 /* 102 * Start addresses for the final memory configuration 103 * (Set up by the startup code) 104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 105 */ 106 #define CONFIG_SYS_SDRAM_BASE 0x40000000 107 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 108 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 109 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 110 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 111 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 112 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 113 114 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 115 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 116 117 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 118 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 119 120 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 121 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 122 123 /* 124 * For booting Linux, the board info and command line data 125 * have to be in the first 8 MB of memory, since this is 126 * the maximum mapped by the Linux kernel during initialization ?? 127 */ 128 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 129 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 130 131 /* FLASH organization */ 132 #define CONFIG_SYS_FLASH_CFI 133 #ifdef CONFIG_SYS_FLASH_CFI 134 # define CONFIG_FLASH_CFI_DRIVER 1 135 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 136 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 137 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 138 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 139 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 140 #endif 141 142 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 143 144 /* 145 * Configuration for environment 146 * Environment is embedded in u-boot in the second sector of the flash 147 */ 148 #define CONFIG_ENV_OFFSET 0x2000 149 #define CONFIG_ENV_SIZE 0x1000 150 #define CONFIG_ENV_SECT_SIZE 0x2000 151 152 #define LDS_BOARD_TEXT \ 153 . = DEFINED(env_offset) ? env_offset : .; \ 154 env/embedded.o(.text*); 155 156 /* Cache Configuration */ 157 #define CONFIG_SYS_CACHELINE_SIZE 16 158 159 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 160 CONFIG_SYS_INIT_RAM_SIZE - 8) 161 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 162 CONFIG_SYS_INIT_RAM_SIZE - 4) 163 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 164 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 165 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 166 CF_ACR_EN | CF_ACR_SM_ALL) 167 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 168 CF_CACR_DISD | CF_CACR_INVI | \ 169 CF_CACR_CEIB | CF_CACR_DCM | \ 170 CF_CACR_EUSP) 171 172 /* Chipselect bank definitions */ 173 /* 174 * CS0 - NOR Flash 175 * CS1 - Available 176 * CS2 - Available 177 * CS3 - Available 178 * CS4 - Available 179 * CS5 - Available 180 */ 181 #define CONFIG_SYS_CS0_BASE 0 182 #define CONFIG_SYS_CS0_MASK 0x007F0001 183 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 184 185 #endif /* _M5208EVBE_H */ 186