1 /* 2 * Configuation settings for the Freescale MCF5208EVBe. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _M5208EVBE_H 11 #define _M5208EVBE_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_MCFUART 18 #define CONFIG_SYS_UART_PORT (0) 19 #define CONFIG_BAUDRATE 115200 20 21 #undef CONFIG_WATCHDOG 22 #define CONFIG_WATCHDOG_TIMEOUT 5000 23 24 /* Command line configuration */ 25 #include <config_cmd_default.h> 26 27 #define CONFIG_CMD_CACHE 28 #define CONFIG_CMD_ELF 29 #define CONFIG_CMD_FLASH 30 #undef CONFIG_CMD_I2C 31 #define CONFIG_CMD_MEMORY 32 #define CONFIG_CMD_MISC 33 #define CONFIG_CMD_MII 34 #define CONFIG_CMD_NET 35 #define CONFIG_CMD_PING 36 #define CONFIG_CMD_REGINFO 37 38 #define CONFIG_MCFFEC 39 #ifdef CONFIG_MCFFEC 40 # define CONFIG_MII 1 41 # define CONFIG_MII_INIT 1 42 # define CONFIG_SYS_DISCOVER_PHY 43 # define CONFIG_SYS_RX_ETH_BUFFER 8 44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 # define CONFIG_HAS_ETH1 46 47 # define CONFIG_SYS_FEC0_PINMUX 0 48 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 49 # define MCFFEC_TOUT_LOOP 50000 50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 51 # ifndef CONFIG_SYS_DISCOVER_PHY 52 # define FECDUPLEX FULL 53 # define FECSPEED _100BASET 54 # else 55 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 # endif 58 # endif /* CONFIG_SYS_DISCOVER_PHY */ 59 #endif 60 61 /* Timer */ 62 #define CONFIG_MCFTMR 63 #undef CONFIG_MCFPIT 64 65 /* I2C */ 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_I2C_FSL 68 #define CONFIG_SYS_FSL_I2C_SPEED 80000 69 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 70 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 71 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 72 73 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 74 #define CONFIG_UDP_CHECKSUM 75 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_IPADDR 192.162.1.2 78 # define CONFIG_NETMASK 255.255.255.0 79 # define CONFIG_SERVERIP 192.162.1.1 80 # define CONFIG_GATEWAYIP 192.162.1.1 81 #endif /* CONFIG_MCFFEC */ 82 83 #define CONFIG_HOSTNAME M5208EVBe 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "loadaddr=40010000\0" \ 87 "u-boot=u-boot.bin\0" \ 88 "load=tftp ${loadaddr) ${u-boot}\0" \ 89 "upd=run load; run prog\0" \ 90 "prog=prot off 0 3ffff;" \ 91 "era 0 3ffff;" \ 92 "cp.b ${loadaddr} 0 ${filesize};" \ 93 "save\0" \ 94 "" 95 96 #define CONFIG_PRAM 512 /* 512 KB */ 97 #define CONFIG_SYS_PROMPT "-> " 98 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 99 100 #ifdef CONFIG_CMD_KGDB 101 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 102 #else 103 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 104 #endif 105 106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 107 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 108 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 109 #define CONFIG_SYS_LOAD_ADDR 0x40010000 110 111 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 112 #define CONFIG_SYS_PLL_ODR 0x36 113 #define CONFIG_SYS_PLL_FDR 0x7D 114 115 #define CONFIG_SYS_MBAR 0xFC000000 116 117 /* 118 * Low Level Configuration Settings 119 * (address mappings, register initial values, etc.) 120 * You should know what you are doing if you make changes here. 121 */ 122 /* Definitions for initial stack pointer and data area (in DPRAM) */ 123 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 124 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 125 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 126 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 127 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 128 129 /* 130 * Start addresses for the final memory configuration 131 * (Set up by the startup code) 132 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 133 */ 134 #define CONFIG_SYS_SDRAM_BASE 0x40000000 135 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 136 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 137 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 138 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 139 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 140 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 141 142 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 143 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 144 145 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 146 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 147 148 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 149 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 150 151 /* 152 * For booting Linux, the board info and command line data 153 * have to be in the first 8 MB of memory, since this is 154 * the maximum mapped by the Linux kernel during initialization ?? 155 */ 156 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 157 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 158 159 /* FLASH organization */ 160 #define CONFIG_SYS_FLASH_CFI 161 #ifdef CONFIG_SYS_FLASH_CFI 162 # define CONFIG_FLASH_CFI_DRIVER 1 163 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 164 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 165 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 166 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 167 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 168 #endif 169 170 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 171 172 /* 173 * Configuration for environment 174 * Environment is embedded in u-boot in the second sector of the flash 175 */ 176 #define CONFIG_ENV_OFFSET 0x2000 177 #define CONFIG_ENV_SIZE 0x1000 178 #define CONFIG_ENV_SECT_SIZE 0x2000 179 #define CONFIG_ENV_IS_IN_FLASH 1 180 181 #define LDS_BOARD_TEXT \ 182 . = DEFINED(env_offset) ? env_offset : .; \ 183 common/env_embedded.o (.text*); 184 185 /* Cache Configuration */ 186 #define CONFIG_SYS_CACHELINE_SIZE 16 187 188 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 189 CONFIG_SYS_INIT_RAM_SIZE - 8) 190 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 191 CONFIG_SYS_INIT_RAM_SIZE - 4) 192 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 193 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 194 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 195 CF_ACR_EN | CF_ACR_SM_ALL) 196 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 197 CF_CACR_DISD | CF_CACR_INVI | \ 198 CF_CACR_CEIB | CF_CACR_DCM | \ 199 CF_CACR_EUSP) 200 201 /* Chipselect bank definitions */ 202 /* 203 * CS0 - NOR Flash 204 * CS1 - Available 205 * CS2 - Available 206 * CS3 - Available 207 * CS4 - Available 208 * CS5 - Available 209 */ 210 #define CONFIG_SYS_CS0_BASE 0 211 #define CONFIG_SYS_CS0_MASK 0x007F0001 212 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 213 214 #endif /* _M5208EVBE_H */ 215